{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:35:04Z","timestamp":1761647704761},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2009,11,1]],"date-time":"2009-11-01T00:00:00Z","timestamp":1257033600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1109\/tcsii.2009.2029144","type":"journal-article","created":{"date-parts":[[2009,11,3]],"date-time":"2009-11-03T18:37:26Z","timestamp":1257273446000},"page":"865-869","source":"Crossref","is-referenced-by-count":16,"title":["A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories"],"prefix":"10.1109","volume":"56","author":[{"family":"Wang Xueqiang","sequence":"first","affiliation":[]},{"family":"Pan Liyang","sequence":"additional","affiliation":[]},{"family":"Wu Dong","sequence":"additional","affiliation":[]},{"family":"Hu Chaohong","sequence":"additional","affiliation":[]},{"family":"Zhou Runde","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","author":"rao","year":"1989","journal-title":"Error-control coding for computer systems"},{"key":"ref3","first-page":"497","article-title":"a 4 gb 2 b\/cell nand flash memory with embedded 5 b bch ecc for 36 mb\/s system read throughput","author":"micheloni","year":"2006","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.354942"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/82.633444"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.916028"},{"key":"ref5","author":"peterson","year":"1972","journal-title":"Error-Correcting Code"},{"key":"ref8","year":"1998","journal-title":"Method and apparatus for correcting a multilevel cell memory by using interleaving"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/76.212719"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.881212"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810782"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811709"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/5337790\/05299022.pdf?arnumber=5299022","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:19Z","timestamp":1633910359000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5299022\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":11,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2009.2029144","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,11]]}}}