{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:27:02Z","timestamp":1772119622769,"version":"3.50.1"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2009,11,1]],"date-time":"2009-11-01T00:00:00Z","timestamp":1257033600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1109\/tcsii.2009.2032470","type":"journal-article","created":{"date-parts":[[2009,11,6]],"date-time":"2009-11-06T21:06:44Z","timestamp":1257541604000},"page":"835-839","source":"Crossref","is-referenced-by-count":95,"title":["Noise Analysis and Minimization in Bang-Bang Digital PLLs"],"prefix":"10.1109","volume":"56","author":[{"given":"M.","family":"Zanuso","sequence":"first","affiliation":[]},{"given":"D.","family":"Tasca","sequence":"additional","affiliation":[]},{"given":"S.","family":"Levantino","sequence":"additional","affiliation":[]},{"given":"A.","family":"Donadel","sequence":"additional","affiliation":[]},{"given":"C.","family":"Samori","sequence":"additional","affiliation":[]},{"given":"A.L.","family":"Lacaita","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","author":"walker","year":"2003","journal-title":"Phase-Locking in High Performance Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/26.506392"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.840089"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.819070"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831600"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.883197"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.906171"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.924371"},{"key":"ref1","first-page":"94","article-title":"bang-bang digital plls at 11 and 20 ghz with sub-200 fs integrated jitter for high speed serial communication applications","author":"rylyakov","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/5337790\/05308247.pdf?arnumber=5308247","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:58:52Z","timestamp":1633910332000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5308247\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":10,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2009.2032470","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,11]]}}}