{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,27]],"date-time":"2024-07-27T22:37:35Z","timestamp":1722119855760},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2010,3,1]],"date-time":"2010-03-01T00:00:00Z","timestamp":1267401600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/tcsii.2010.2040302","type":"journal-article","created":{"date-parts":[[2010,3,9]],"date-time":"2010-03-09T16:50:24Z","timestamp":1268153424000},"page":"198-202","source":"Crossref","is-referenced-by-count":16,"title":["Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes"],"prefix":"10.1109","volume":"57","author":[{"family":"Tso-Bing Juang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chin-Chieh Chiu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ming-Yu Tsai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"364","article-title":"implementation of rsa algorithm based on rns montgomery multiplication","volume":"2162","author":"nozaki","year":"2001","journal-title":"Proc 3rd Int Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1976.1162834"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"158","DOI":"10.1109\/ARITH.1999.762841","article-title":"efficient vlsi implementation of modulo <ref_formula><tex notation=\"tex\">$2^{n}\\pm 1$<\/tex><\/ref_formula> addition and multiplication","author":"zimmermann","year":"1999","journal-title":"Proc 14th IEEE Symp Comput Arithmetic"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1146705"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1244938"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.923413"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015352"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2001964"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2008.22"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219822"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.921068"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2000.951651"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378155"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2001.987709"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVT.2002.804850"},{"key":"ref7","first-page":"472","article-title":"fast rns fpl-based communications receiver design and implementation","volume":"2438","author":"ramrez","year":"2002","journal-title":"Proc 12th Int Conf Field Programmable Logic"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/el:20020192"},{"key":"ref1","author":"soderstrand","year":"1986","journal-title":"Residue Number System Arithmetic Modern Applications in Digital Signal Processing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TWC.2004.833509"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"387","DOI":"10.1145\/1142155.1142162","article-title":"on the construction of zero-deficiency parallel prefix circuits with minimum depth","volume":"11","author":"zhu","year":"2006","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.817789"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675982"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/5437388\/05427119.pdf?arnumber=5427119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:47:23Z","timestamp":1633913243000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5427119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":22,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2010.2040302","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,3]]}}}