{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,2]],"date-time":"2026-03-02T10:57:56Z","timestamp":1772449076496,"version":"3.50.1"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2010,5,1]],"date-time":"2010-05-01T00:00:00Z","timestamp":1272672000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/tcsii.2010.2047311","type":"journal-article","created":{"date-parts":[[2010,5,21]],"date-time":"2010-05-21T20:58:26Z","timestamp":1274475506000},"page":"324-328","source":"Crossref","is-referenced-by-count":32,"title":["A 5-Gb\/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications"],"prefix":"10.1109","volume":"57","author":[{"family":"Kuo-Hsing Cheng","sequence":"first","affiliation":[]},{"family":"Yu-Chang Tsai","sequence":"additional","affiliation":[]},{"family":"Yen-Hsueh Wu","sequence":"additional","affiliation":[]},{"family":"Ying-Fu Lin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845563"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2010177"},{"key":"ref12","year":"2009","journal-title":"PCI Express Base Specification Gen2 Rev 2 1"},{"key":"ref13","author":"johns","year":"1997","journal-title":"Analog Integrated Circuit Design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903076"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822774"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857354"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2023299"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880629"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705378"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1998.694995"},{"key":"ref1","author":"razavi","year":"2002","journal-title":"Design of Integrated Circuits for Optical Communications"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005535"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/5466561\/05462962.pdf?arnumber=5462962","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:43:59Z","timestamp":1633913039000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5462962\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":13,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2010.2047311","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,5]]}}}