{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T09:13:57Z","timestamp":1775121237066,"version":"3.50.1"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2011,3,1]],"date-time":"2011-03-01T00:00:00Z","timestamp":1298937600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/tcsii.2011.2110370","type":"journal-article","created":{"date-parts":[[2011,3,15]],"date-time":"2011-03-15T17:09:34Z","timestamp":1300208974000},"page":"149-153","source":"Crossref","is-referenced-by-count":10,"title":["Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology"],"prefix":"10.1109","volume":"58","author":[{"given":"Ching-Che","family":"Chung","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chiun-Yao","family":"Ko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung-En","family":"Shen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042250"},{"key":"ref3","first-page":"267","article-title":"A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory","author":"hsu","year":"2008","journal-title":"Proc IEEE VLSI-DAT"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.926793"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031577"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2011577"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2044903"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.846307"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.818579"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"525","DOI":"10.1109\/TCSII.2009.2020948","article-title":"A leakage-compensated PLL in 65-nm CMOS technology","volume":"56","author":"hung","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.903782"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022916"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/5730542\/05730479.pdf?arnumber=5730479","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:23Z","timestamp":1633909943000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5730479\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":11,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2011.2110370","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,3]]}}}