{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T12:52:02Z","timestamp":1756385522880},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/tcsii.2012.2184371","type":"journal-article","created":{"date-parts":[[2012,2,3]],"date-time":"2012-02-03T21:01:24Z","timestamp":1328302884000},"page":"88-92","source":"Crossref","is-referenced-by-count":9,"title":["Embedded Analog Nonvolatile Memory With Bidirectional and Linear Programmability"],"prefix":"10.1109","volume":"59","author":[{"given":"Yi-Da","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kok-Choon","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chih-Cheng","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hsin","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/5.993402"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.846663"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2011.2109000"},{"key":"ref13","author":"cauwenberghs","year":"1999","journal-title":"Learning on Silicon Adaptive VLSI Neural Systems"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"1758","DOI":"10.1109\/4.726571","article-title":"An 8-bit-resolution, 360-<ref_formula><tex Notation=\"TeX\">$\\mu$<\/tex><\/ref_formula>s write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)","volume":"33","author":"kim","year":"1998","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1328209"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880621"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.523872"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/82.913181"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/16.239745"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/55.31687"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2006642"},{"key":"ref27","first-page":"990","article-title":"Self learning analog neural network LSI with high-resolution nonvolatile analog memory and a partially serial weight-update architecture","volume":"e 80c","author":"morie","year":"1997","journal-title":"IEICE Trans Electron"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/55.75728"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/82.913189"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"2584","DOI":"10.1109\/TCSI.2008.918010","article-title":"A 1.2-GHz comparator with adaptable offset in 0.35- <ref_formula><tex Notation=\"TeX\">$\\mu\\hbox{m}$<\/tex> <\/ref_formula> CMOS","volume":"55","author":"wong","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/82.913187"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/16.644652"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488619"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/82.913188"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.1989.118698"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.400434"},{"key":"ref22","first-page":"93","article-title":"New single-poly EEPROM with cell size down to <ref_formula><tex Notation=\"TeX\">$8{\\rm F}^{2}$<\/tex><\/ref_formula> for high density embedded nonvolatile memory applications","author":"lee","year":"2003","journal-title":"Proc Symp VLSI Tech"},{"key":"ref21","first-page":"441","article-title":"On-chip compensation of device-mismatch effects in analog VLSI neural networks","author":"figueroa","year":"2004","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1049\/ip-vis:20030362"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.859648"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2042677"},{"key":"ref25","first-page":"2487","article-title":"A log-domain implementation of the diffusion network in very large scale integration","author":"wu","year":"2010","journal-title":"Proc Adv Neural Inf Process Syst"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/6155183\/06145623.pdf?arnumber=6145623","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:53:19Z","timestamp":1633909999000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6145623\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":28,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2012.2184371","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,2]]}}}