{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,30]],"date-time":"2026-07-30T14:14:03Z","timestamp":1785420843191,"version":"3.56.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/tcsii.2012.2222837","type":"journal-article","created":{"date-parts":[[2012,11,21]],"date-time":"2012-11-21T20:10:15Z","timestamp":1353528615000},"page":"741-745","source":"Crossref","is-referenced-by-count":12,"title":["A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash\u2013SAR Architecture"],"prefix":"10.1109","volume":"59","author":[{"given":"Young-Deuk","family":"Jeon","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jae-Won","family":"Nam","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kwi-Dong","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tae Moon","family":"Roh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jong-Kee","family":"Kwon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"309","article-title":"A 52 mW 10 b 210 MS\/s two-step ADC for digital-IF receivers in 0.13 <ref_formula><tex Notation=\"TeX\">$\\mu \\hbox{m}$<\/tex><\/ref_formula> CMOS","author":"cao","year":"2008","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873888"},{"key":"ref10","first-page":"466","article-title":"A 1.7 mW 11 b 250 MS\/s <ref_formula><tex Notation=\"TeX\">$2\\times$<\/tex><\/ref_formula> interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS","author":"verbruggen","year":"2012","journal-title":"Proc IEEE ISSCC Tech Dig"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"502","DOI":"10.1109\/TCSII.2010.2048387","article-title":"A 9-bit 80 MS\/s successive approximation register analog-to-digital converter with a capacitor reduction technique","volume":"57","author":"cho","year":"2010","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref5","first-page":"386","article-title":"A 10 b 100 MS\/s 1.13 mW SAR ADC with binary-scaled error compensation","author":"liu","year":"2010","journal-title":"Proc IEEE ISSCC Tech Dig"},{"key":"ref12","first-page":"473","article-title":"A 9.15 mW 0.22 <ref_formula><tex Notation=\"TeX\">$\\hbox{mm}^{2}$<\/tex><\/ref_formula> 10 b 204 MS\/s pipelined SAR ADC in 65 nm CMOS","author":"jeon","year":"2010","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2126390"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref2","first-page":"462","article-title":"A 92.5 mW 205 MS\/s 10 b pipeline IF ADC implemented in 1.2 V\/3.3 V 0.13 <ref_formula><tex Notation=\"TeX\">$\\mu \\hbox{m}$<\/tex><\/ref_formula> CMOS","author":"hernes","year":"2007","journal-title":"Proc IEEE ISSCC Tech Dig"},{"key":"ref9","first-page":"61","article-title":"A 35 fJ 10 b 160 MS\/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation","author":"zhu","year":"2011","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"2688","DOI":"10.1109\/JSSC.2007.908760","article-title":"A 10-bit 205 MS\/s 1.0-<ref_formula><tex Notation=\"TeX\">$\\hbox{mm}^{2}$<\/tex><\/ref_formula> 90-nm CMOS pipeline ADC for flat panel display applications","volume":"42","author":"lee","year":"2007","journal-title":"IEEE J Solid-State Circuits"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/6403559\/06352867.pdf?arnumber=6352867","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:44:20Z","timestamp":1638218660000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6352867\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":12,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2012.2222837","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,11]]}}}