{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,10]],"date-time":"2026-05-10T03:08:11Z","timestamp":1778382491071,"version":"3.51.4"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/tcsii.2012.2228398","type":"journal-article","created":{"date-parts":[[2012,12,19]],"date-time":"2012-12-19T19:42:53Z","timestamp":1355946173000},"page":"790-794","source":"Crossref","is-referenced-by-count":17,"title":["A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances"],"prefix":"10.1109","volume":"59","author":[{"given":"Jui-Jen","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shau-Wei","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Lo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Quincy","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001872"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2083130"},{"key":"ref12","first-page":"266","article-title":"A 0.29 V embedded NAND-ROM in 90 nm CMOS for ultra-low-voltage applications","author":"chang","year":"2010","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1657","DOI":"10.1109\/TCSI.2008.2010101","article-title":"Wide-VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems","volume":"56","author":"chang","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"ref15","first-page":"156","article-title":"A differential data aware power-supplied <ref_formula><tex Notation=\"TeX\">$(\\hbox{D}_{2}\\hbox{AP})$<\/tex> <\/ref_formula> 8T SRAM cell with expanded write\/read stabilities for lower VDDmin applications","author":"chang","year":"2009","journal-title":"Proc Symp VLSI Circuits Dig Tech Papers"},{"key":"ref16","first-page":"211","article-title":"A 45 nm dual-port SRAM with write and read capability enhancement at low voltage","author":"wang","year":"2007","journal-title":"SoC Conf Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831461"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.784095"},{"key":"ref6","first-page":"130","article-title":"A 65 nm ultra-high-density dual port SRAM with 0.71 &#x03BC;m2 8 T cell for SoC","author":"nii","year":"2006","journal-title":"Proc IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705286"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560339"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013766"},{"key":"ref2","first-page":"669","article-title":"Efficient macroblock pipeline structure in high definition AVS video encoder VLSI architecture","author":"yin","year":"2010","journal-title":"Proc IEEE ISCAS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.875323"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2010.5716538"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/6403559\/06387586.pdf?arnumber=6387586","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:44:21Z","timestamp":1638218661000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6387586\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":16,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2012.2228398","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,11]]}}}