{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T17:55:16Z","timestamp":1649094916761},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tcsii.2014.2327340","type":"journal-article","created":{"date-parts":[[2014,5,30]],"date-time":"2014-05-30T18:23:31Z","timestamp":1401474211000},"page":"466-470","source":"Crossref","is-referenced-by-count":2,"title":["A 4.1-mW 3.5-GS\/s 6-Bit Time-Interleaved ADC in 40-nm CMOS"],"prefix":"10.1109","volume":"61","author":[{"given":"Annachiara","family":"Spagnolo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bob","family":"Verbruggen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Piet","family":"Wambacq","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefano","family":"D'Amico","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"-264c","article-title":"An 8.5 mW 5 GS\/s 6b Flash ADC with dynamic offset calibration in 32 nm CMOS SOI","author":"chen","year":"0","journal-title":"Proc VLSI Symp"},{"key":"ref3","first-page":"26","article-title":"A 6b 3GS\/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators","author":"shu","year":"0","journal-title":"Proc VLSI Symp"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2168020"},{"key":"ref5","first-page":"-260c","article-title":"A 35 mW 8b 8.8 GS\/s SAR ADC with low-power capacitive reference buffers in 32 nm digital SOI CMOS","author":"kull","year":"0","journal-title":"Proc VLSI Symp"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1829","DOI":"10.1109\/TCSI.2009.2037403","article-title":"An asynchronous binary-search ADC architecture with a reduced comparator count","volume":"57","author":"lin","year":"2010","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006315"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2061611"},{"key":"ref9","first-page":"269","article-title":"A low-noise self-calibrating dynamic comparator for high-speed ADCs","author":"miyahara","year":"0","journal-title":"Proc IEEE A-SSCC"},{"key":"ref1","first-page":"230","article-title":"A fully integrated 60 GHz CMOS transceiver chipset based on WiGig\/IEEE802.11ad with built-in self calibration for mobile applications","author":"tsukizawa","year":"0","journal-title":"Proc IEEE ISSCC Tech Dig"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/6856260\/06823685.pdf?arnumber=6823685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:16:56Z","timestamp":1642004216000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6823685\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":9,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2014.2327340","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}