{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,18]],"date-time":"2026-01-18T13:33:13Z","timestamp":1768743193362,"version":"3.49.0"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2014,11,1]],"date-time":"2014-11-01T00:00:00Z","timestamp":1414800000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2008-0062617"],"award-info":[{"award-number":["2008-0062617"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003836","name":"IC Design Education Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/tcsii.2014.2350378","type":"journal-article","created":{"date-parts":[[2014,8,22]],"date-time":"2014-08-22T19:47:53Z","timestamp":1408736873000},"page":"840-844","source":"Crossref","is-referenced-by-count":12,"title":["A 0.5-V, 1.47- $\\mu\\hbox{W}$ 40-kS\/s 13-bit SAR ADC With Capacitor Error Compensation"],"prefix":"10.1109","volume":"61","author":[{"given":"Hyunsoo","family":"Ha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seon-Kyoo","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"380","article-title":"A 12 b 22.5\/45 MS\/s 3.0 mW 0.059 $\\hbox{mm}^{2}$ CMOS SAR ADC achieving over 90 dB SFDR","author":"liu","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref11","first-page":"238","article-title":"An 820 $\\mu\\hbox{W}$ 9 b 40 MS\/s noise-tolerant dynamic SAR ADC in 90 nm digital CMOS","author":"giannini","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref12","first-page":"272","article-title":"A 71 dB-SNDR 50 MS\/s 4.2 mW CMOS SAR ADC by SNR enhancement techniques utilizing noise","author":"morie","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref13","first-page":"472","article-title":"A 14 b 80 MS\/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS","author":"kapusta","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref14","first-page":"1","article-title":"A 24 mW 12 b 1 MS\/s 68.3 dB SNDR SAR ADC with two-step decision DAC switching","author":"chung","year":"0","journal-title":"Proc CICC"},{"key":"ref4","first-page":"388","article-title":"A 30 fJ\/conversion-step 8 b 0-to-10 MS\/s asynchronous SAR ADC in 90 nm CMOS","author":"harpe","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"222","article-title":"A 25 $\\mu\\hbox{W}$ 100 kS\/s 12 b ADC for wireless micro-sensor applications","author":"verma","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref6","first-page":"270","article-title":"A 2.2\/2.7 fJ\/conversion-step 10\/12 bit 40 kS\/s SAR ADC with data-driven noise reduction","author":"harpe","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref5","author":"murmann","year":"0","journal-title":"ADC Performance Survey 1997&#x2013;2013"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280859"},{"key":"ref7","first-page":"384","article-title":"A 10 b 50 MS\/s 820 $\\mu\\hbox{W}$ SAR ADC with on-chip digital calibration","author":"yoshioka","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"246","article-title":"A 9.4-ENOB 1 V 3.8 $\\mu\\hbox{W}$ 100 kS\/s SAR ADC with time-domain comparator","author":"agnes","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"242","article-title":"A 1.3 $\\mu\\hbox{W}$ 0.6 V 8.7-ENOB successive approximation ADC in a 0.18 $\\mu\\hbox{W}$ CMOS","author":"lee","year":"0","journal-title":"VLSI Symp Tech Dig"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2252475"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/6945398\/06882154.pdf?arnumber=6882154","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:06:14Z","timestamp":1642003574000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6882154\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":14,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2014.2350378","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,11]]}}}