{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:32:42Z","timestamp":1761895962109},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/tcsii.2014.2368259","type":"journal-article","created":{"date-parts":[[2014,11,7]],"date-time":"2014-11-07T19:56:06Z","timestamp":1415390166000},"page":"236-240","source":"Crossref","is-referenced-by-count":15,"title":["A Low-Voltage Sense Amplifier for Embedded Flash Memories"],"prefix":"10.1109","volume":"62","author":[{"given":"Hua","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Ling","family":"Lu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"125003","DOI":"10.1088\/1674-4926\/32\/12\/125003","article-title":"A new low-voltage and high-speed sense amplifier for flash memory","volume":"32","author":"jiarong","year":"2011","journal-title":"Chin J Semicond"},{"key":"ref11","first-page":"434","article-title":"A 0.5 V 4 Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low-voltage current-mode sensing scheme with 45 ns random read time","author":"chang","year":"0","journal-title":"Proc IEEE ISSCC"},{"key":"ref12","first-page":"428","article-title":"Bitline-capacitance-cancelation sensing scheme with 11 ns read latency and maximum read throughput of 2.9 GB\/s in 65 nm embedded flash for automotive","author":"jefremow","year":"0","journal-title":"Proc IEEE ISSCC"},{"key":"ref13","first-page":"212","article-title":"40 nm embedded SG-MONOS flash macros for automotive with 160 MHz random access for code and endurance over 10 M cycles for data","author":"kono","year":"0","journal-title":"Proc IEEE ISSCC"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.974549"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.881211"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.871317"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/82.847079"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.840985"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845564"},{"key":"ref2","author":"roy","year":"2000","journal-title":"Low Power CMOS VLSI Circuit Design"},{"key":"ref1","author":"haraszti","year":"2001","journal-title":"CMOS Memory Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/31\/10\/105001"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7051297\/06949685.pdf?arnumber=6949685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:40:53Z","timestamp":1642005653000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6949685\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":13,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2014.2368259","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3]]}}}