{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,8]],"date-time":"2026-06-08T15:56:48Z","timestamp":1780934208431,"version":"3.54.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003621","name":"Ministry of Science, ICT and Future Planning","doi-asserted-by":"publisher","award":["GFP\/(CISS-2011-0031860)"],"award-info":[{"award-number":["GFP\/(CISS-2011-0031860)"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Korea IT R&D program of the Ministry of Trade, Industry and Energy\/Korea Evaluation Institute of Industrial Technology","award":["KI10035202"],"award-info":[{"award-number":["KI10035202"]}]},{"DOI":"10.13039\/501100003836","name":"IC Design Education Center","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/tcsii.2014.2369131","type":"journal-article","created":{"date-parts":[[2014,11,10]],"date-time":"2014-11-10T14:25:20Z","timestamp":1415629520000},"page":"306-310","source":"Crossref","is-referenced-by-count":35,"title":["Partially Parallel Encoder Architecture for Long Polar Codes"],"prefix":"10.1109","volume":"62","author":[{"given":"Hoyoung","family":"Yoo","sequence":"first","affiliation":[{"name":"Dept. of Electr. Eng., Korea Adv. Inst. of Sci. &amp; Technol., Daejeon, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"In-Cheol","family":"Park","sequence":"additional","affiliation":[{"name":"Dept. of Electr. Eng., Korea Adv. Inst. of Sci. &amp; Technol., Daejeon, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2012.2223693"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/GlobalSIP.2013.6737143"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2014.140515"},{"key":"ref13","article-title":"Low-latency successive-cancellation list decoders for polar codes with multibit decision","author":"yuan","year":"0","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2291065"},{"key":"ref15","author":"parhi","year":"1999","journal-title":"VLSI Digital Signal Processing Systems Design and Implementation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/82.300209"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.365120"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2147338"},{"key":"ref19","author":"wang","year":"1992","journal-title":"MARS A high-level synthesis tool for digital signal processing architecture design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2011.6033904"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2010.2080990"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCNC.2013.6504198"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2013.070213.120789"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2013.6674541"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2014.140514"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2009.090428"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2009.2021379"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2283779"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7051297\/06951410.pdf?arnumber=6951410","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T01:08:19Z","timestamp":1755911299000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6951410\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":19,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2014.2369131","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3]]}}}