{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,27]],"date-time":"2025-11-27T16:12:00Z","timestamp":1764259920289},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2015,6,1]],"date-time":"2015-06-01T00:00:00Z","timestamp":1433116800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/tcsii.2015.2407792","type":"journal-article","created":{"date-parts":[[2015,2,27]],"date-time":"2015-02-27T19:34:21Z","timestamp":1425065661000},"page":"593-597","source":"Crossref","is-referenced-by-count":9,"title":["A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric"],"prefix":"10.1109","volume":"62","author":[{"given":"Wen","family":"Yueh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Subho","family":"Chatterjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muneeb","family":"Zia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saibal","family":"Mukhopadhyay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"474","article-title":"A 3 GHz 70 Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply","volume":"1","author":"zhang","year":"0","journal-title":"Proc IEEE ISSCC"},{"key":"ref11","article-title":"Predictive Technology Model (PTM)","year":"0"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1147\/rd.475.0553"},{"key":"ref13","first-page":"1","article-title":"22 nm technology compatible fully functional 0.1 µm 2 6T SRAM cell","author":"haran","year":"0","journal-title":"Proc IEEE IEDM"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2372034"},{"key":"ref3","article-title":"Designing a coarse-grained reconfigurable architecture for power efficiency","author":"carroll","year":"2007"},{"key":"ref6","first-page":"77","article-title":"MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices","author":"paul","year":"0","journal-title":"Proc Asia South Pacific Des Autom Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1995.518231"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687431"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950481"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275138"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226362"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7115238\/07051284.pdf?arnumber=7051284","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:02:24Z","timestamp":1642003344000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7051284\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":13,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2015.2407792","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6]]}}}