{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,6]],"date-time":"2022-04-06T03:43:56Z","timestamp":1649216636460},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/tcsii.2015.2436151","type":"journal-article","created":{"date-parts":[[2015,5,21]],"date-time":"2015-05-21T18:46:48Z","timestamp":1432234008000},"page":"856-860","source":"Crossref","is-referenced-by-count":1,"title":["Accelerated Dual-Path Asynchronous Circuit"],"prefix":"10.1109","volume":"62","author":[{"given":"Tiben","family":"Che","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jingwei","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gwan","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1645","article-title":"Multi-rate layered decoder architecture for block LDPC codes of the IEEE 802.11 n wireless standard","author":"gunnam","year":"0","journal-title":"Proc IEEE ISCAS"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9317(00)80065-9"},{"key":"ref12","author":"spars","year":"2002","journal-title":"Principles of Asynchronous Circuits Design"},{"key":"ref13","author":"friesenbichler","year":"2011","journal-title":"Effects and mitigation of transient faults in quasi delay-insensitive logic"},{"key":"ref14","first-page":"100","article-title":"Cost-effective radiation hardening technique for combinational logic","author":"zhou","year":"0","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E92.C.867"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/APEMC.2010.5475640"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2014.6908544"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311875"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.44"},{"key":"ref7","first-page":"863","article-title":"Asynchronous circuits transient faults sensitivity evaluation","author":"monnet","year":"0","journal-title":"42nd Annu Des Autom Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860958"},{"key":"ref1","first-page":"1","article-title":"Asynchronous circuit design—A tutorial","author":"sparso","year":"2006","journal-title":"Chapters 1–8 in Principles of Asynchronous Circuit Design —A Systems Perspective"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5029-z"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7229390\/07111250.pdf?arnumber=7111250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:03:47Z","timestamp":1642003427000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7111250"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":14,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2015.2436151","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9]]}}}