{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T05:06:17Z","timestamp":1769922377267,"version":"3.49.0"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T00:00:00Z","timestamp":1454284800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Ministry of Science, ICT and Future Planning (MSIP), Korea, under the Information Technology Research Center (ITRC) support program","award":["IITP-2015-H8501-15-1002"],"award-info":[{"award-number":["IITP-2015-H8501-15-1002"]}]},{"name":"Institute for Information & communications Technology Promotion (IITP)"},{"name":"National Research Foundation of the MSIP, Korea","award":["2014-052875"],"award-info":[{"award-number":["2014-052875"]}]},{"DOI":"10.13039\/501100003836","name":"IDEC","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2016,2]]},"DOI":"10.1109\/tcsii.2015.2468911","type":"journal-article","created":{"date-parts":[[2015,8,14]],"date-time":"2015-08-14T14:39:10Z","timestamp":1439563150000},"page":"141-145","source":"Crossref","is-referenced-by-count":24,"title":["A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%\u201380% Input Duty Cycle for SDRAMs"],"prefix":"10.1109","volume":"63","author":[{"given":"Ji-Hoon","family":"Lim","sequence":"first","affiliation":[]},{"given":"Jun-Hyun","family":"Bae","sequence":"additional","affiliation":[]},{"given":"Jaemin","family":"Jang","sequence":"additional","affiliation":[]},{"given":"Hae-Kang","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Hyunbae","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Yongju","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[]},{"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2291052"},{"key":"ref3","first-page":"283","article-title":"A low cost high performance register-controlled digital DLL for 1 Gb\/s × 32 DDR SDRAM","author":"kwak","year":"0","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref10","first-page":"547","article-title":"A 2.5 Gb\/s\/pin 256 Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop digital DLL","author":"lee","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref6","first-page":"2007","article-title":"An all-digital 90-degree phase-shift DLL with loop embedded DCC for 1.6 Gb\/s DDR interface","author":"bae","year":"0","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.889381"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.882186"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2182216"},{"key":"ref2","first-page":"282","article-title":"A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66 nm CMOS technology","author":"yun","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2014.14.4.457"},{"key":"ref1","first-page":"341","article-title":"A 0.1–1.5 GHz all-digital phase inversion delay-locked loop","author":"han","year":"0","journal-title":"Proc IEEE Asian Solid State Circuits Conf"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7394206\/7202853.pdf?arnumber=7202853","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:48:36Z","timestamp":1641988116000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7202853"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2]]},"references-count":10,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2015.2468911","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,2]]}}}