{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T19:58:35Z","timestamp":1740167915103,"version":"3.37.3"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61306023"],"award-info":[{"award-number":["61306023"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"State Key Lab of ASIC & System","award":["2015MS006"],"award-info":[{"award-number":["2015MS006"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/tcsii.2015.2468915","type":"journal-article","created":{"date-parts":[[2015,8,14]],"date-time":"2015-08-14T14:39:10Z","timestamp":1439563150000},"page":"1139-1143","source":"Crossref","is-referenced-by-count":8,"title":["A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT\/IDCT in HEVC Encoders Based on Single-Port SRAMs"],"prefix":"10.1109","volume":"62","author":[{"given":"Yibo","family":"Fan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leilei","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yufeng","family":"Bai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyang","family":"Zeng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/SPL.2012.6211786"},{"key":"ref11","first-page":"2634","article-title":"41.7BN-pixels\/s reconfigurable intra prediction architecture for HEVC 2560 $\\times$ 1600 encoder","author":"liu","year":"0","journal-title":"Proc IEEE ICASSP"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/PCS.2013.6737693"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/IPAS.2014.7043303"},{"key":"ref14","first-page":"154","article-title":"A 4320p 60 fps H.264\/AVC intra-frame encoder chip with 1.41 Gbins\/s CABAC","author":"zhou","year":"0","journal-title":"Proc Symp VLSI Circuits"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ICE-CCN.2013.6528494"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TCSVT.2014.2337572"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/ICCE-Berlin.2013.6698026"},{"key":"ref18","first-page":"1509","article-title":"A deblocking filter hardware architecture for the high efficiency video coding standard","author":"diniz","year":"0","journal-title":"Proc DATE"},{"key":"ref19","first-page":"673","article-title":"A high-throughput VLSI architecture for deblocking filter in HEVC","author":"shen","year":"0","journal-title":"Proc IEEE ISCAS"},{"key":"ref4","first-page":"1","article-title":"A cost effective implementation of 8 $\\times$ 8 transform of HEVC from H.264\/AVC","author":"martuza","year":"0","journal-title":"Proc IEEE CCECE"},{"key":"ref3","first-page":"1290","article-title":"A cost effective 2-D adaptive block size IDCT architecture for HEVC standard","author":"liang","year":"0","journal-title":"Proc IEEE 56th Int MWSCAS"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ISPACS.2012.6473512"},{"key":"ref5","first-page":"405","article-title":"Content adaptive prediction unit size decision algorithm for HEVC intra coding","author":"tian","year":"0","journal-title":"Proc PCS"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/TCE.2014.7027352"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ISIEA.2013.6738966"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/VCIP.2014.7051538"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/TCSVT.2013.2276862"},{"key":"ref9","first-page":"677","article-title":"Fully pipelined DCT\/IDCT\/Hadamard unified transform architecture for HEVC codec","author":"zhu","year":"0","journal-title":"Proc IEEE ISCAS"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1145\/2024724.2024951"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7337508\/07202845.pdf?arnumber=7202845","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:46:52Z","timestamp":1641988012000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7202845"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":20,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2015.2468915","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2015,12]]}}}