{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:09:10Z","timestamp":1761581350893},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/tcsii.2015.2482618","type":"journal-article","created":{"date-parts":[[2015,9,28]],"date-time":"2015-09-28T18:28:33Z","timestamp":1443464913000},"page":"244-248","source":"Crossref","is-referenced-by-count":22,"title":["A 12.5-ENOB 10-kS\/s Redundant SAR ADC in 65-nm CMOS"],"prefix":"10.1109","volume":"63","author":[{"given":"Dai","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Atila","family":"Alvandpour","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.50301"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274113"},{"key":"ref12","first-page":"284","article-title":"A 14b 35 MS\/s SAR ADC achieving 75 dB SNDR and 99 dB SFDR with loop-embedded input buffer in 40 nm CMOS","author":"kr\u00e4mer","year":"0","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref13","first-page":"1","article-title":"An 18b 5 MS\/s SAR ADC with 100.2 dB dynamic range","author":"bannon","year":"0","journal-title":"Proc VLSI Symp"},{"key":"ref14","author":"murmann","year":"0","journal-title":"ADC Performance Survey 1997&#x2013;2013"},{"key":"ref4","first-page":"194","article-title":"An oversampled 12\/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1 dB SNDR","author":"harpe","year":"0","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"272","article-title":"A 71 dB-SNDR 50 MS\/s 4.2 mW CMOS SAR ADC by SNR enhancement techniques utilizing noise","author":"morie","year":"0","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341331"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2163556"},{"key":"ref8","first-page":"62","article-title":"An error-correcting $14\\mbox{b}\/20\\ \\mu\\mbox{s}$ CMOS A\/D converter","author":"boyacigiller","year":"0","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2331111"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052231"},{"key":"ref1","article-title":"TI HealthTech health guide","year":"2013"},{"key":"ref9","author":"razavi","year":"2001","journal-title":"Design of Analog CMOS Integrated Circuits"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7420760\/7279120.pdf?arnumber=7279120","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:48:24Z","timestamp":1642006104000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7279120\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":14,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2015.2482618","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,3]]}}}