{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,4]],"date-time":"2024-07-04T10:40:17Z","timestamp":1720089617780},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/tcsii.2016.2536258","type":"journal-article","created":{"date-parts":[[2016,2,29]],"date-time":"2016-02-29T19:23:24Z","timestamp":1456773804000},"page":"964-968","source":"Crossref","is-referenced-by-count":9,"title":["Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution"],"prefix":"10.1109","volume":"63","author":[{"given":"Kiryong","family":"Kim","sequence":"first","affiliation":[]},{"given":"Hanwool","family":"Jeong","sequence":"additional","affiliation":[]},{"given":"Juhyun","family":"Park","sequence":"additional","affiliation":[]},{"given":"Seong-Ook","family":"Jung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"310","article-title":"A 0.6 V 1.5 GHz 84 Mb SRAM design in 14 nm FinFET CMOS technology","author":"karl","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref11","first-page":"238","article-title":"A 16 nm 128 Mb SRAM in high- $\\kappa$ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications","author":"chen","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref12","first-page":"234","article-title":"Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM","author":"kulkarni","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654259"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424366"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2012.6251663"},{"key":"ref17","first-page":"12","article-title":"FinFET performance advantage at 22 nm: An AC perspective","author":"guillorn","year":"0","journal-title":"Proc Symp VLSI Technol"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2010.04.010"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2388837"},{"key":"ref4","first-page":"316","article-title":"A 20 nm 112Mb SRAM in High- $\\kappa$ metal-gate with assist circuitry for low-leakage and low-VMIN applications","author":"chang","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"232","article-title":"A 14 nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications","author":"song","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref6","first-page":"1","article-title":"Scaling of 32 nm low power SRAM with high-K metal gate","author":"yang","year":"0","journal-title":"Proc IEDM Dig Tech Papers"},{"key":"ref5","first-page":"230","article-title":"A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"karl","year":"0","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231015"},{"key":"ref7","first-page":"1","article-title":"The impact of assist-circuit design for 22 nm SRAM and beyond","author":"karl","year":"0","journal-title":"Proc IEDM Dig Tech Papers"},{"key":"ref2","first-page":"16","article-title":"Modeling of width quantization induced variations in logic FinFETs for 22 nm and beyond","author":"lin","year":"0","journal-title":"Proc Symp VLSI Technol"},{"key":"ref1","first-page":"131","article-title":"A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors","author":"auth","year":"0","journal-title":"Proc Symp VLSI Technol"},{"key":"ref9","first-page":"254","article-title":"A 64Mb SRAM in 32 nm High-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements","author":"pilo","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7574395\/07422039.pdf?arnumber=7422039","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:20:57Z","timestamp":1642004457000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7422039\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":19,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2016.2536258","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,10]]}}}