{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T19:57:44Z","timestamp":1740167864055,"version":"3.37.3"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003848","name":"Industrial Technology Research Institute","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003848","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007225","name":"Ministry of Science and Technology","doi-asserted-by":"publisher","award":["NSC 102-2221-E-009-177-MY3"],"award-info":[{"award-number":["NSC 102-2221-E-009-177-MY3"]}],"id":[{"id":"10.13039\/100007225","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/tcsii.2016.2539038","type":"journal-article","created":{"date-parts":[[2016,3,7]],"date-time":"2016-03-07T19:09:20Z","timestamp":1457377760000},"page":"969-973","source":"Crossref","is-referenced-by-count":3,"title":["Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations"],"prefix":"10.1109","volume":"63","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4598-7123","authenticated-orcid":false,"given":"Po-Hao","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Chung","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Hui","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tang-Chieh","family":"Kao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi-Lun","family":"Tsai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pei-Yao","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tay-Jyi","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinn-Shyan","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tien-Fu","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"article-title":"Circuit for determining the number of logical one values on a data bus","year":"2004","author":"hossain","key":"ref11"},{"key":"ref12","first-page":"118","article-title":"New hardware architecture for bit-counting","author":"dalalah","year":"0","journal-title":"Proc 5th WSEAS Int Conf Appl Comput Sci"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1062261.1062321"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"article-title":"Dinero IV trace-driven uniprocessor cache simulator","year":"2003","author":"edler","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref19","article-title":"Exploring CoreMark—A benchmark maximizing simplicity and efficacy","author":"gal-on","year":"2012","journal-title":"The Embedded Microprocessor Benchmark Consortium"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000118"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0390"},{"journal-title":"Error Control Coding","year":"2004","author":"lin","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"ref1","first-page":"158","article-title":"A 0.48 V 0.57 nJ\/pixel video-recording SoC in 65 nm CMOS","author":"lin","year":"0","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/358274.358283"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7574395\/07426799.pdf?arnumber=7426799","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:20:57Z","timestamp":1642004457000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7426799\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":20,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2016.2539038","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2016,10]]}}}