{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:39:39Z","timestamp":1781887179283,"version":"3.54.5"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2017,6,1]],"date-time":"2017-06-01T00:00:00Z","timestamp":1496275200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2017,6]]},"DOI":"10.1109\/tcsii.2016.2594827","type":"journal-article","created":{"date-parts":[[2016,7,27]],"date-time":"2016-07-27T14:44:36Z","timestamp":1469630676000},"page":"700-704","source":"Crossref","is-referenced-by-count":61,"title":["A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area"],"prefix":"10.1109","volume":"64","author":[{"given":"Byungkyu","family":"Song","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Taehui","family":"Na","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jung Pill","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seung H.","family":"Kang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0757-2581","authenticated-orcid":false,"given":"Seong-Ook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"318","article-title":"A 3T1R nonvolatile TCAM using MLC ReRAM with sub-1 ns search time","author":"chang","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273541"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2292055"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2316241"},{"key":"ref14","first-page":"279","article-title":"45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T\/1MTJ cell","author":"lin","year":"0","journal-title":"Proc IEEE IEDM Tech Dig"},{"key":"ref15","first-page":"1","article-title":"Toggle and spin torque: MRAM at Everspin technologies","author":"rizzo","year":"0","journal-title":"Proc Non-Volatile Memories Workshop"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239320"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2020935"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914330"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274888"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239092"},{"key":"ref8","first-page":"289","article-title":"Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control","author":"matsunaga","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref7","first-page":"240","article-title":"A 28 nm 400 MHz 4-parallel 1.6 Gsearch\/s 80 Mb ternary CAM","author":"nii","year":"0","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2082950"},{"key":"ref1","first-page":"122","article-title":"ReRAM-based 4T2R nonvolatile TCAM with 7&#x00D7; NVM-stress reduction, and 4&#x00D7; improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing","author":"huang","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref9","first-page":"44","article-title":"A 3.14 $\\mu\\text{m}^{2}$ 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture","author":"matsunaga","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits Dig Tech Papers"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7934201\/07523965.pdf?arnumber=7523965","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:40:23Z","timestamp":1641987623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7523965\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6]]},"references-count":16,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2016.2594827","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,6]]}}}