{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T19:57:48Z","timestamp":1740167868930,"version":"3.37.3"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["MOST 105-2221-E-002-198-MY3"],"award-info":[{"award-number":["MOST 105-2221-E-002-198-MY3"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NTU Excellent Research Project","award":["105R0062-01"],"award-info":[{"award-number":["105R0062-01"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/tcsii.2016.2608908","type":"journal-article","created":{"date-parts":[[2016,9,13]],"date-time":"2016-09-13T18:13:39Z","timestamp":1473790419000},"page":"1166-1170","source":"Crossref","is-referenced-by-count":6,"title":["A 12.5-fJ\/Conversion-Step 8-Bit 800-MS\/s Two-Step SAR ADC"],"prefix":"10.1109","volume":"63","author":[{"given":"Yao-Sheng","family":"Hu","sequence":"first","affiliation":[]},{"given":"Po-Chao","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Hung-Yen","family":"Tai","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7666-4984","authenticated-orcid":false,"given":"Hsin-Shu","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2211695"},{"key":"ref11","first-page":"200","article-title":"11.4 A 1.5 mW 68 dB SNDR 80 MS\/s $2\\times $ interleaved SAR-assisted pipelined ADC in 28 nm CMOS","author":"van der goes","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"339","DOI":"10.1109\/TCSII.2014.2312642","article-title":"A 6-bit 1-GS\/s two-step SAR ADC in 40-nm CMOS","volume":"61","author":"tai","year":"2014","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref13","first-page":"386","article-title":"A 10 b 100 MS\/s 1.13 mW SAR ADC with binary-scaled error compensation","author":"liu","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2503705"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"journal-title":"Design of Analog CMOS Integrated Circuits","year":"2000","author":"razavi","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243803"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243802"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523298"},{"key":"ref3","first-page":"274c","article-title":"A 6b 10GS\/s TI-SAR ADC with embedded 2-tap FFE\/1-tap DFE in 65nm CMOS","author":"tabasy","year":"2013","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2015.7387462"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2364833"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2204543"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref2","first-page":"260c","article-title":"A 35mW8 b 8.8 GS\/s SAR ADC with low-power capacitive reference buffers in 32nm digital SOI CMOS","author":"kull","year":"2013","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref1","first-page":"378","article-title":"22 1 A 90GS\/s 8b 667mW $64\\times $ interleaved SAR ADC in 32nm digital SOI CMOS","author":"kull","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7752994\/07565573.pdf?arnumber=7565573","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:21:01Z","timestamp":1642004461000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7565573\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":18,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2016.2608908","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2016,12]]}}}