{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:49:24Z","timestamp":1761562164601,"version":"3.37.3"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/tcsii.2016.2624145","type":"journal-article","created":{"date-parts":[[2016,11,1]],"date-time":"2016-11-01T18:13:54Z","timestamp":1478024034000},"page":"1111-1115","source":"Crossref","is-referenced-by-count":5,"title":["Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs"],"prefix":"10.1109","volume":"63","author":[{"given":"Valerio","family":"Tenace","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5881-3811","authenticated-orcid":false,"given":"Andrea","family":"Calimera","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Enrico","family":"Macii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Massimo","family":"Poncino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.853601"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744880"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837496"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.05.018"},{"key":"ref14","first-page":"1","article-title":"Pass-XNOR logic: A new logic style for P–N junction based graphene circuits","author":"tenace","year":"2014","journal-title":"Proc IEEE Des Autom Test Europe Conf Exhib (DATE)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1021\/nl102756r"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1021\/nn103221v"},{"key":"ref17","first-page":"877","article-title":"A verilog-a model for reconfigurable logic gates based on graphene pn-junctions","author":"miryala","year":"2013","journal-title":"Proc Conf DATE"},{"key":"ref18","first-page":"1","article-title":"Decision diagrams and pass transistor logic synthesis","volume":"168","author":"bertacco","year":"1997","journal-title":"Proc Int Workshop Logic Synth"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-45711-5_1"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2014.49"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2415177"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.245595"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MWC.2010.5675779"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.597298"},{"key":"ref7","first-page":"220","article-title":"Application of dynamic pass-transistor logic to an 8-bit multiplier","volume":"38","author":"lee","year":"2001","journal-title":"J Korean Phys Soc"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/82.633443"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547542"},{"key":"ref9","first-page":"1","article-title":"Low-leakage and low-power implementation of high-speed 65nm logic gates","author":"wu","year":"2008","journal-title":"Proc EDSSC"},{"journal-title":"Biconditional Binary Decision Diagrams Software Package","year":"2016","key":"ref20"},{"journal-title":"CUDD CU Decision Diagram Package Release 2 3 0","year":"1998","author":"somenzi","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2902970"},{"journal-title":"Collection of Digital Design Benchmarks","year":"2016","key":"ref23"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/7752994\/07728047.pdf?arnumber=7728047","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:21:01Z","timestamp":1642004461000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7728047\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":23,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2016.2624145","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2016,12]]}}}