{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T19:57:39Z","timestamp":1740167859752,"version":"3.37.3"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61401090","61704088"],"award-info":[{"award-number":["61401090","61704088"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/tcsii.2019.2913023","type":"journal-article","created":{"date-parts":[[2019,4,24]],"date-time":"2019-04-24T20:07:36Z","timestamp":1556136456000},"page":"455-459","source":"Crossref","is-referenced-by-count":4,"title":["A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5957-3207","authenticated-orcid":false,"given":"Chenggang","family":"Yan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7878-498X","authenticated-orcid":false,"given":"Jianhui","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Sun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4102-6077","authenticated-orcid":false,"given":"Jin","family":"Jin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"26","article-title":"A 2.5GHz delay-based wideband OFDM outphasing modulator in 45nm-LP CMOS","author":"ravi","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref11","first-page":"360","article-title":"21.1 a 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC","author":"marucci","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831608"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2551598"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005702"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2650407"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2321200"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2688384"},{"key":"ref6","first-page":"1","article-title":"14.1 a 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique","author":"deng","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804339"},{"key":"ref8","first-page":"272","article-title":"15.4 a 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS","author":"elkholy","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2620151"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2017.2697879"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2196315"},{"key":"ref9","first-page":"268","article-title":"15.2 a 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider","author":"liu","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9016282\/08698328.pdf?arnumber=8698328","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T16:53:57Z","timestamp":1651078437000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8698328\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":15,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2019.2913023","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2020,3]]}}}