{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T19:17:21Z","timestamp":1769282241491,"version":"3.49.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/tcsii.2019.2915377","type":"journal-article","created":{"date-parts":[[2019,5,8]],"date-time":"2019-05-08T00:47:11Z","timestamp":1557276431000},"page":"531-535","source":"Crossref","is-referenced-by-count":26,"title":["A Quasi-V<sup>2<\/sup> Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8998-221X","authenticated-orcid":false,"given":"Chung-Yi","family":"Ting","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9539-4975","authenticated-orcid":false,"given":"Jing-Yuan","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Charlie Chung-Ping","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2466791"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2012.2230649"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2346770"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2018.2833062"},{"key":"ref11","author":"baker","year":"1998","journal-title":"CMOS Circuit Design Layout and Simulation"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2805884"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820870"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2865643"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2883889"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2464720"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157253"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2063610"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9016282\/08708292.pdf?arnumber=8708292","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T16:53:57Z","timestamp":1651078437000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8708292\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":12,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2019.2915377","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,3]]}}}