{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,12]],"date-time":"2026-05-12T16:53:57Z","timestamp":1778604837529,"version":"3.51.4"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000006","name":"Office of Naval Research","doi-asserted-by":"publisher","award":["N00014-18-1-2254"],"award-info":[{"award-number":["N00014-18-1-2254"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/tcsii.2020.3012386","type":"journal-article","created":{"date-parts":[[2020,7,27]],"date-time":"2020-07-27T21:14:12Z","timestamp":1595884452000},"page":"106-110","source":"Crossref","is-referenced-by-count":31,"title":["Neural-Network Based Self-Initializing Algorithm for Multi-Parameter Optimization of High-Speed ADCs"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4818-3366","authenticated-orcid":false,"given":"Shrestha","family":"Bansal","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5519-8048","authenticated-orcid":false,"given":"Erfan","family":"Ghaderi","sequence":"additional","affiliation":[]},{"given":"Chase","family":"Puglisi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4754-3451","authenticated-orcid":false,"given":"Subhanshu","family":"Gupta","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2006.18.7.1527"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2870529"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2662085"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063011"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICNN.1995.488968"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2863959"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2016.7905422"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063106"},{"key":"ref18","first-page":"622","article-title":"Neurally-guided procedural models: Amortized inference for procedural graphics programs using neural networks","author":"ritchie","year":"2016","journal-title":"Proc Int Conf Neural Inf Process"},{"key":"ref19","first-page":"170","article-title":"An integrated MaxFit genetic algorithm-SPICE framework for 2-stage op-amp design automation","author":"v","year":"2018","journal-title":"Proc IEEE Computer Soc Annu Symp VLSI (ISVLSI)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2603442"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/82.850422"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2015.7282149"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2011.5946799"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SIS.2005.1501648"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.916408"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/82.554434"},{"key":"ref1","first-page":"914","article-title":"Fast nonlinear deterministic calibration of pipelined A\/D converters","author":"oshima","year":"2008","journal-title":"Proc IEEE Midwest Symp Circuits Syst (MWSCAS)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TAP.1976.1141414"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s10107-015-0864-7"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SIS.2003.1202255"},{"key":"ref21","author":"allstot","year":"2003","journal-title":"Parasitic-Aware Optimization of CMOS RF Circuits"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-7908-2604-3_16"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s10107-012-0572-5"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9301450\/09149914.pdf?arnumber=9149914","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:52:16Z","timestamp":1652194336000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9149914\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":24,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2020.3012386","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}