{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T19:57:59Z","timestamp":1740167879923,"version":"3.37.3"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada (NSERC) HIDATA Project","doi-asserted-by":"publisher","award":["506289-2017"],"award-info":[{"award-number":["506289-2017"]}],"id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ERC-CoG IONOS N de convention de subvention","award":["773228"],"award-info":[{"award-number":["773228"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/tcsii.2020.3026642","type":"journal-article","created":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T20:23:35Z","timestamp":1600979015000},"page":"1128-1132","source":"Crossref","is-referenced-by-count":6,"title":["AIDX: Adaptive Inference Scheme to Mitigate State-Drift in Memristive VMM Accelerators"],"prefix":"10.1109","volume":"68","author":[{"given":"Tony","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amirali","family":"Amirsoleimani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabien","family":"Alibart","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Serge","family":"Ecoffey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dominique","family":"Drouin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Genov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6165062"},{"key":"ref3","first-page":"148","article-title":"A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)","author":"chen","year":"2010","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1002\/9781118445112.stat02299"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203824"},{"journal-title":"PROBN1-A Set of Benchmarks and benchmarking rules for neural-network training algorithms","year":"1994","author":"prechelt","key":"ref11"},{"key":"ref5","first-page":"242","article-title":"Memristor-based approximated computation","author":"li","year":"2013","journal-title":"Proc Int Symp Low-Power Electronics Design"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3371277"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433536"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1002\/aelm.201700561"},{"key":"ref2","first-page":"200","article-title":"A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability","author":"sheu","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"journal-title":"Practical Methods of Optimization","year":"2013","author":"fletcher","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1021\/nn202983n"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9387428\/09205289.pdf?arnumber=9205289","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:52:18Z","timestamp":1652194338000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9205289\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":12,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2020.3026642","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}