{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T15:18:32Z","timestamp":1772205512222,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","award":["JZ2020HGTA0085"],"award-info":[{"award-number":["JZ2020HGTA0085"]}],"id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","award":["JZ2020HGQA0162"],"award-info":[{"award-number":["JZ2020HGQA0162"]}],"id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/tcsii.2020.3039532","type":"journal-article","created":{"date-parts":[[2020,11,20]],"date-time":"2020-11-20T20:30:04Z","timestamp":1605904204000},"page":"1233-1237","source":"Crossref","is-referenced-by-count":9,"title":["Spars: A Full Flow Quantum-Dot Cellular Automata Circuit Design Tool"],"prefix":"10.1109","volume":"68","author":[{"given":"Fei","family":"Peng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongqiang","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Kuang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guangjun","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"ref11","author":"soeken","year":"2019","journal-title":"The EPFL logic synthesis libraries"},{"key":"ref12","first-page":"1","article-title":"Boolean logic optimization in majority-inverter graphs","author":"amar\u00fa","year":"2015","journal-title":"Proc 52nd ACM\/EDAC\/IEEE Design Autom Conf (DAC)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/1097-007X(200101\/02)29:1<49::AID-CTA132>3.0.CO;2-1"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907020"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2471996"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538997"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560130"},{"key":"ref18","author":"peng","year":"0","journal-title":"A gate level placement and routing algorithm for QCA circuit"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.07.011"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938081"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.820815"},{"key":"ref6","author":"walter","year":"2019","journal-title":"fiction An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789782"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3338852.3339838"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1063\/1.354535"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-43722-3","author":"anderson","year":"2014","journal-title":"Field-Coupled Nanocomputing"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1063\/1.356375"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/s10825-016-0804-7"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1063\/1.1368389"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.004"},{"key":"ref23","first-page":"1774","article-title":"Performance analysis and design of full adder in quantum-dot cellular automata","volume":"46","author":"sun","year":"2018","journal-title":"ACTA Electron Sinica"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2012.6321982"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9387428\/09265404.pdf?arnumber=9265404","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,29]],"date-time":"2022-11-29T04:00:32Z","timestamp":1669694432000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9265404\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":25,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2020.3039532","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}