{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,13]],"date-time":"2026-07-13T11:02:23Z","timestamp":1783940543997,"version":"3.55.0"},"reference-count":82,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003246","name":"Dutch NWO Project","doi-asserted-by":"publisher","award":["14714 BrainWave"],"award-info":[{"award-number":["14714 BrainWave"]}],"id":[{"id":"10.13039\/501100003246","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/tcsii.2020.3040970","type":"journal-article","created":{"date-parts":[[2020,11,30]],"date-time":"2020-11-30T20:54:56Z","timestamp":1606769696000},"page":"5-11","source":"Crossref","is-referenced-by-count":15,"title":["Twenty Years of Near\/Sub-Threshold Design Trends and Enablement"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9382-6068","authenticated-orcid":false,"given":"Kamlesh","family":"Singh","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0723-7065","authenticated-orcid":false,"given":"Jose","family":"Pineda de Gyvez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842861"},{"key":"ref72","doi-asserted-by":"crossref","first-page":"930","DOI":"10.1109\/JSSC.2016.2519386","article-title":"A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI","volume":"51","author":"zimmer","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2690859"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/PESC.2007.4342378"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2633805"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00039"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973093"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487801"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274829"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934635"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2637003"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2831665"},{"key":"ref33","first-page":"1","article-title":"A 0.5V 2.5?W\/MHz microcontroller with analog-assisted adaptive body bias PVT compensation with 3.13nW\/kB SRAM retention in 55nm deeply-depleted channel CMOS","author":"pons","year":"2019","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref32","first-page":"322","article-title":"A 40-to-80MHz sub-4?W\/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with dual-loop adaptive back-bias generator for 20?s wake-up from deep fully retentive sleep mode","author":"bol","year":"2019","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494312"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2821167"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2039684"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063136"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662454"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662486"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654219"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820873"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176932"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638465"},{"key":"ref64","doi-asserted-by":"crossref","DOI":"10.1109\/S3S46989.2019.9320687","article-title":"Power and variation improved near-Vth standard cell library for 28-nm FDSOI","author":"wong","year":"2019","journal-title":"Proc IEEE SOI 3D Subthreshold Microelectron Technol Unified Conf"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2693241"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147022"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/92.920822"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494259"},{"key":"ref67","doi-asserted-by":"crossref","first-page":"355","DOI":"10.1145\/1283780.1283857","article-title":"Vt balancing and device sizing towards high yield of sub-threshold static logic gates","author":"pu","year":"2007","journal-title":"Proc ACM\/IEEE Int Symp Low Power Electron Design"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228533"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2016.2530745"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.604077"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177101"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2233352"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2218067"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062967"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231307"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008529"},{"key":"ref25","first-page":"1","article-title":"A 0.33V\/?40°C process\/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing","author":"clerc","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2158124"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428045"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2135550"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.60"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/EEEI.2008.4736624"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063078"},{"key":"ref55","first-page":"88","article-title":"An 85% efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range","author":"salem","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2014.6908567"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417956"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/CoolChips.2016.7503670"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2198984"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220671"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2102571"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC46988.2019.1570558508"},{"key":"ref16","first-page":"51","article-title":"A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist","author":"chiu","year":"2013","journal-title":"Proc Int Symp Low-Power Electronics Design"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357018"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332267"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007160"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014205"},{"key":"ref80","article-title":"Converter free power delivery using voltage stacking for near\/sub-threshold operation","author":"singh","year":"0","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035453"},{"key":"ref6","year":"2020","journal-title":"Everactive"},{"key":"ref5","year":"2020","journal-title":"Ambiq Micro Inc"},{"key":"ref8","first-page":"154","article-title":"A 2.60pJ\/inst subthreshold sensor processor for optimal energy efficiency","author":"zhai","year":"2006","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332709"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2959544"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342694"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2897016"},{"key":"ref45","first-page":"1","article-title":"A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI","author":"blagojevi?","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502411"},{"key":"ref47","first-page":"304","article-title":"A 2.5?W 0.0067mm² automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range","author":"quelen","year":"2018","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283789"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757511"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2014.7008858"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2060503"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9301450\/09273082.pdf?arnumber=9273082","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,14]],"date-time":"2023-10-14T08:22:37Z","timestamp":1697271757000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9273082\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":82,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2020.3040970","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}