{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T14:02:46Z","timestamp":1773842566833,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2021,11]]},"DOI":"10.1109\/tcsii.2021.3077669","type":"journal-article","created":{"date-parts":[[2021,5,5]],"date-time":"2021-05-05T20:34:45Z","timestamp":1620246885000},"page":"3456-3460","source":"Crossref","is-referenced-by-count":13,"title":["Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1363-9201","authenticated-orcid":false,"given":"S.","family":"Perri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2197-4563","authenticated-orcid":false,"given":"F.","family":"Spagnolo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5795-4321","authenticated-orcid":false,"given":"F.","family":"Frustaci","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9528-1110","authenticated-orcid":false,"given":"P.","family":"Corsonello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2261831"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2012.2220565"},{"key":"ref12","article-title":"BCD adder designs based on three-input XOR and majority gates","author":"chu","year":"2020","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2953866"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2295711"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8350962"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2018.2836918"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2019.2929100"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050819"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789782"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2953617"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2881326"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2910137"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2999131"},{"key":"ref8","first-page":"223","volume":"8280","author":"vacca","year":"2014","journal-title":"NanoMagnet Logic An Architectural Level Overview"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/5.573740"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2865783"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569370"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2054120"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.146"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2471996"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907020"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR.2010.579"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2306754"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/9590087\/09424144.pdf?arnumber=9424144","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:52:26Z","timestamp":1652194346000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9424144\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11]]},"references-count":24,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2021.3077669","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11]]}}}