{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T19:58:26Z","timestamp":1740167906702,"version":"3.37.3"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2023,3]]},"DOI":"10.1109\/tcsii.2022.3222001","type":"journal-article","created":{"date-parts":[[2022,11,15]],"date-time":"2022-11-15T20:38:13Z","timestamp":1668544693000},"page":"1134-1138","source":"Crossref","is-referenced-by-count":0,"title":["Design and Testing of Digital Logic Gates Using HCS Macro-Model"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7002-3115","authenticated-orcid":false,"given":"Snigdha Chowdhury","family":"Kolay","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Camellia School of Engineering and Technology, Kolkata, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6790-8150","authenticated-orcid":false,"given":"Mandakinee","family":"Bandyopadhyay","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Institute of Engineering and Management, Kolkata, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2852-1169","authenticated-orcid":false,"given":"Subrata","family":"Chattopadhyay","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Institute of Technical Teachers’ Training and Research Kolkata, Kolkata, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"42","article-title":"Carbon nanotubes-production, properties and health effects","volume":"5","author":"Ziauddin","year":"2014","journal-title":"Int. J. Adv. Eng. Technol."},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/ijch.201900026"},{"key":"ref3","first-page":"4499","article-title":"Mathematical modeling and analysis of dynamic response of RTD using MATLAB","volume":"4","author":"Sawai","year":"2015","journal-title":"Int. J. Adv. Res. Electr. Electron. Instrum. Eng."},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/77.107400"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.813909"},{"key":"ref6","first-page":"36","article-title":"A review towards single electron transistor (SET)","volume":"4","author":"Goyal","year":"2015","journal-title":"Int. J. Adv. Res. Comput. Commun. Eng."},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2012.11.001"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TE.2002.1024612"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1063\/1.360107"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1155\/1998\/19218"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.658562"},{"volume-title":"KOSEC (KOrea Single Electron Circuit simulator) is Developed in the Nanoelectronics","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.11591\/ij-nano.v1i2.1518"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-015-0491-5"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2009.5418646"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TIC-STH.2009.5444535"},{"issue":"2","key":"ref17","first-page":"1907","article-title":"Single electron transistor and its simulation methods","volume":"2","author":"Sinha","year":"2014","journal-title":"Int. J. Eng. Develop. Res."},{"issue":"2","key":"ref18","first-page":"1","article-title":"Design and implementation of a hybrid SET-CMOS based sequential circuit","volume":"4","author":"Jana","year":"2012","journal-title":"J. Nano Electron. Phys."}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/10061496\/09951401.pdf?arnumber=9951401","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T03:07:57Z","timestamp":1706756877000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9951401\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3]]},"references-count":18,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2022.3222001","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2023,3]]}}}