{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T20:07:48Z","timestamp":1769544468283,"version":"3.49.0"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"Spanish Research Agency through the Project AgileMon","award":["AEI PID2019-104451RB-C21"],"award-info":[{"award-number":["AEI PID2019-104451RB-C21"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2023,7]]},"DOI":"10.1109\/tcsii.2023.3237736","type":"journal-article","created":{"date-parts":[[2023,1,18]],"date-time":"2023-01-18T13:38:41Z","timestamp":1674049121000},"page":"2620-2624","source":"Crossref","is-referenced-by-count":0,"title":["Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8632-9146","authenticated-orcid":false,"given":"Tob\u00edas","family":"Alonso","sequence":"first","affiliation":[{"name":"High Performance Computing and Networking Research Group, Escuela Polit&#x00E9;cnica Superior, Universidad Aut&#x00F3;noma de Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8820-5956","authenticated-orcid":false,"given":"Gustavo","family":"Sutter","sequence":"additional","affiliation":[{"name":"High Performance Computing and Networking Research Group, Escuela Polit&#x00E9;cnica Superior, Universidad Aut&#x00F3;noma de Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4057-4688","authenticated-orcid":false,"given":"Sergio","family":"L\u00f3pez-Buedo","sequence":"additional","affiliation":[{"name":"High Performance Computing and Networking Research Group, Escuela Polit&#x00E9;cnica Superior, Universidad Aut&#x00F3;noma de Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jorge E. L\u00f3pez","family":"de Vergara","sequence":"additional","affiliation":[{"name":"High Performance Computing and Networking Research Group, Escuela Polit&#x00E9;cnica Superior, Universidad Aut&#x00F3;noma de Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW50202.2020.00020"},{"key":"ref12","year":"2021","journal-title":"Vitis High-Level Synthesis User Guide Version V2021 1"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012866"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488796"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOMW.2015.7414014"},{"key":"ref11","year":"2021","journal-title":"Intel high level synthesis compiler pro edition Reference manual"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01720-9"},{"key":"ref10","year":"2021","journal-title":"Catapult HLS"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-800056-4.00007-8"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123471"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/197405.197406"},{"key":"ref17","year":"2022","journal-title":"Publication repository"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021754"},{"key":"ref19","article-title":"The universality of Zipf&#x2019;s law for time-dependent rank-based random systems","author":"fernholz","year":"2017","journal-title":"arXiv 1707 04285"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/83.855427"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/12.24269"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/rd.111.0025"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195534"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132715"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1007516818651"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2783363"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.31"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/10164655\/10021278.pdf?arnumber=10021278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T06:09:29Z","timestamp":1769494169000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10021278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7]]},"references-count":22,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2023.3237736","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,7]]}}}