{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,20]],"date-time":"2025-07-20T04:25:46Z","timestamp":1752985546503,"version":"3.37.3"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002367","name":"Strategic Priority Research Program of Chinese Academy of Sciences: Standardization Research and System Development of SEANET Technology","doi-asserted-by":"publisher","award":["XDC02070100"],"award-info":[{"award-number":["XDC02070100"]}],"id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]},{"name":"IACAS Frontier Exploration Project"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2024,1]]},"DOI":"10.1109\/tcsii.2023.3304014","type":"journal-article","created":{"date-parts":[[2023,8,10]],"date-time":"2023-08-10T17:54:17Z","timestamp":1691690057000},"page":"420-424","source":"Crossref","is-referenced-by-count":3,"title":["Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-8621-2315","authenticated-orcid":false,"given":"Xiaoyong","family":"Song","sequence":"first","affiliation":[{"name":"National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2489-9949","authenticated-orcid":false,"given":"Zhichuan","family":"Guo","sequence":"additional","affiliation":[{"name":"National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, Beijing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2021.09.037"},{"issue":"1","key":"ref2","first-page":"1","article-title":"A survey of TCAM emulation on FPGAs","volume":"12","author":"Huang","year":"2023","journal-title":"Netw. New Media Technol."},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2027946"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2020935"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3014154"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2082950"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ANCS.2013.6665177"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215736"},{"issue":"1","key":"ref9","first-page":"116","article-title":"Updating algorithm for SRAM-based TCAM and its implementation on FPGA","volume":"15","author":"Syed","year":"2017","journal-title":"Int. J. Comput. Sci. Inf. Secur."},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2017.2770225"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3026840"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2020.2999471"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPSR.2013.6602288"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCIC.2013.6724271"},{"year":"2022","key":"ref15","article-title":"BGP analysis reports (IPv4): AS65000 BGP routing table analysis report"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00049"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-79911-2"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2528638"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.2014RCP0006"},{"key":"ref20","first-page":"59","article-title":"An architecture for IPv6 lookup using parallel index generation units","volume-title":"Proc. Reconfigurable Comput.: Architect. Tools Appl.: 9th Int. Symp.","volume":"7806","author":"Hiroki"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3080184"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8920\/10385034\/10214357.pdf?arnumber=10214357","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T00:40:19Z","timestamp":1704847219000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10214357\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1]]},"references-count":21,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2023.3304014","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"type":"print","value":"1549-7747"},{"type":"electronic","value":"1558-3791"}],"subject":[],"published":{"date-parts":[[2024,1]]}}}