{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T02:16:47Z","timestamp":1771467407156,"version":"3.50.1"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","award":["555486-2020"],"award-info":[{"award-number":["555486-2020"]}],"id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2025,8]]},"DOI":"10.1109\/tcsii.2025.3547997","type":"journal-article","created":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T13:56:39Z","timestamp":1741096599000},"page":"978-982","source":"Crossref","is-referenced-by-count":2,"title":["An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb\/s Wireline Systems"],"prefix":"10.1109","volume":"72","author":[{"given":"Richard","family":"Barrie","sequence":"first","affiliation":[{"name":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2739-7496","authenticated-orcid":false,"given":"Ming","family":"Yang","sequence":"additional","affiliation":[{"name":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6247-512X","authenticated-orcid":false,"given":"Hossein","family":"Shakiba","sequence":"additional","affiliation":[{"name":"Huawei Technologies Canada, Markham, ON, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-7516","authenticated-orcid":false,"given":"Anthony Chan","family":"Carusone","sequence":"additional","affiliation":[{"name":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1979.11409"},{"key":"ref2","volume-title":"Error Propagation Analysis of MLSE","author":"Shakiba","year":"2023"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2023.3324602"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ieeestd.2020.9135000"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS60917.2024.10658786"},{"key":"ref6","volume-title":"Concatenated FEC Baseline Proposal for 200Gb\/s Per Lane IM-DD Optical PMD","year":"2023"},{"key":"ref7","volume-title":"Error-Correction Coding for Digital Communications. Applications of Communications Theory","author":"Clark","year":"1981"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1972.1054746"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2943569"},{"key":"ref10","first-page":"1","article-title":"A statistical modeling approach for FEC-encoded high-speed wireline links","volume-title":"Proc. DesignCon","author":"Yang"},{"key":"ref11","first-page":"1","article-title":"Statistical BER analysis of concatenated FEC in multi-part links","volume-title":"Proc. Designcon","author":"Barrie"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3286803"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454537"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.81"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0184406-1"},{"key":"ref16","volume-title":"Concatenated FEC Baseline Proposal for 200Gb\/s Per Lane IM-DD Optical PMD","author":"Farhood","year":"2023"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4899-2174-1"},{"key":"ref18","year":"2023","journal-title":"Proposal for BER Budget Allocation for AUIs in Type 1 and Type 2 PHYs"},{"key":"ref19","author":"Xiang","year":"2023","journal-title":"Low Latency Mode for Inner FEC"},{"key":"ref20","volume-title":"Richard259 FPGA-FEC","author":"Barrie","year":"2025"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8920\/11104806\/10909714.pdf?arnumber=10909714","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T19:07:20Z","timestamp":1764184040000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10909714\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8]]},"references-count":20,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2025.3547997","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,8]]}}}