{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,17]],"date-time":"2026-07-17T18:37:41Z","timestamp":1784313461681,"version":"3.55.0"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274081"],"award-info":[{"award-number":["62274081"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62304099"],"award-info":[{"award-number":["62304099"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"Shenzhen Stable Support Plan Program for Higher Education Institutions Research Program","doi-asserted-by":"publisher","award":["2023QN10X177"],"award-info":[{"award-number":["2023QN10X177"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2025,11]]},"DOI":"10.1109\/tcsii.2025.3583043","type":"journal-article","created":{"date-parts":[[2025,6,25]],"date-time":"2025-06-25T14:26:46Z","timestamp":1750861606000},"page":"1605-1609","source":"Crossref","is-referenced-by-count":8,"title":["Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS"],"prefix":"10.1109","volume":"72","author":[{"given":"Moxiao","family":"Lou","sequence":"first","affiliation":[{"name":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-8174-3542","authenticated-orcid":false,"given":"Jin","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-3508-982X","authenticated-orcid":false,"given":"Humiao","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhengke","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5519-3258","authenticated-orcid":false,"given":"Quan","family":"Cheng","sequence":"additional","affiliation":[{"name":"Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3566-7855","authenticated-orcid":false,"given":"Jiamin","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0377-2108","authenticated-orcid":false,"given":"Masanori","family":"Hashimoto","sequence":"additional","affiliation":[{"name":"Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4702-737X","authenticated-orcid":false,"given":"Longyang","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3332017"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3092759"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2981901"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3241385"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062985"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067422"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3375359"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218567"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365766"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061508"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067555"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904659"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747151"},{"key":"ref19","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"Weste","year":"2010"},{"key":"ref20","volume":"31","author":"Ishibashi","year":"2011","journal-title":"Low Power and Reliable SRAM Memory Cell and Array Design (Series in Advanced Microelectronics)"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8920\/11230143\/11050911.pdf?arnumber=11050911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T19:07:22Z","timestamp":1764184042000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11050911\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11]]},"references-count":20,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2025.3583043","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11]]}}}