{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T18:27:17Z","timestamp":1772908037812,"version":"3.50.1"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"SIU Startup Fund"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. Video Technol."],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/tcsvt.2018.2878399","type":"journal-article","created":{"date-parts":[[2018,10,30]],"date-time":"2018-10-30T08:49:57Z","timestamp":1540889397000},"page":"3415-3429","source":"Crossref","is-referenced-by-count":38,"title":["Efficient Algorithm Adaptations and Fully Parallel Hardware Architecture of H.265\/HEVC Intra Encoder"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6083-2544","authenticated-orcid":false,"given":"Yuanzhi","family":"Zhang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6451-8453","authenticated-orcid":false,"given":"Chao","family":"Lu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2014.6775887"},{"key":"ref11","first-page":"373","article-title":"An efficient VLSI architecture for \n$4\\times4$\n intra prediction in the High Efficiency Video Coding (HEVC) standard","author":"li","year":"2011","journal-title":"Proc ICIP"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2012.6466830"},{"key":"ref13","first-page":"1","article-title":"A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder","author":"liu","year":"2013","journal-title":"Proc Asic"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742917"},{"key":"ref15","first-page":"27","article-title":"A double-path intra prediction architecture for the hardware H.265\/HEVC encoder","author":"abramowski","year":"2014","journal-title":"Proc SDDECS"},{"key":"ref16","first-page":"2634","article-title":"41.7BN-pixels\/s reconfigurable intra prediction architecture for HEVC \n$2560\\times 1600$\n encoder","author":"liu","year":"2013","journal-title":"Proc ICASSP"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/PCS.2013.6737693"},{"key":"ref18","first-page":"188c","article-title":"A 1062 Mpixels\/s \n$8192\\times4320$\np High Efficiency Video Coding (H.265) encoder chip","author":"tsai","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063063"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PCS.2013.6737724"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-319-06895-4","author":"sze","year":"2014","journal-title":"High Efficiency Video Coding (HEVC) Algorithms and Architectures"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2016.12.024"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221525"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2013.2249017"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2016.7760792"},{"key":"ref5","first-page":"56","article-title":"Content based hierarchical fast coding unit decision algorithm for HEVC","author":"leng","year":"2012","journal-title":"Proc of CMS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VCIP.2011.6115979"},{"key":"ref7","first-page":"73","article-title":"Low complexity rate distortion optimization for HEVC","author":"ma","year":"2013","journal-title":"Proc DCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221192"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2013.2290578"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s11554-015-0549-8"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2016.2593618"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2015.2428571"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TMM.2017.2700629"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2017.014728"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2018.2830126"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2006.873160"}],"container-title":["IEEE Transactions on Circuits and Systems for Video Technology"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/76\/8886618\/08513868.pdf?arnumber=8513868","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:12:04Z","timestamp":1657746724000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8513868\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":29,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsvt.2018.2878399","relation":{},"ISSN":["1051-8215","1558-2205"],"issn-type":[{"value":"1051-8215","type":"print"},{"value":"1558-2205","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,11]]}}}