{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T12:47:42Z","timestamp":1767703662699,"version":"3.37.3"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"crossref","award":["TEC2012-38329-C02-02"],"award-info":[{"award-number":["TEC2012-38329-C02-02"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Dependable and Secure Comput."],"published-print":{"date-parts":[[2018,9,1]]},"DOI":"10.1109\/tdsc.2016.2610966","type":"journal-article","created":{"date-parts":[[2016,9,19]],"date-time":"2016-09-19T19:16:06Z","timestamp":1474312566000},"page":"898-905","source":"Crossref","is-referenced-by-count":17,"title":["Hardware Architecture Implemented on FPGA for Protecting Cryptographic Keys against Side-Channel Attacks"],"prefix":"10.1109","volume":"15","author":[{"given":"Ruben","family":"Lumbiarres-Lopez","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5556-233X","authenticated-orcid":false,"given":"Mariano","family":"Lopez-Garcia","sequence":"additional","affiliation":[]},{"given":"Enrique","family":"Canto-Navarro","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.3"},{"key":"ref11","first-page":"1","article-title":"Correlated\n power noise generator as low cost DPA countermeasures to secure hardware AES chiper","author":"kamoun","year":"0","journal-title":"Proc Int Conf Signals Circuits Syst"},{"journal-title":"The Design of Rijndael AES—The Advanced Encryption Standard","year":"2002","author":"daemen","key":"ref12"},{"article-title":"AES proposal: Rijndael","year":"0","author":"daemen","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ifs.2010.0096"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ifs:20070066"},{"key":"ref16","first-page":"224","article-title":"Synthesis of secure FPGA implementations","author":"tiri","year":"0","journal-title":"Proc Int Workshop Logic Synthesis"},{"key":"ref17","first-page":"849","article-title":"BCDL: A high performance balanced DPL with global precharge and\n without early-evaluation","year":"0","journal-title":"Proc Des Autom Test Eur IEEE Comput Soc"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968292"},{"key":"ref4","first-page":"403","article-title":"A dynamic and differential CMOS logic with\n signal independent power consumption to withstand differential power analysis on smart cards","year":"0","journal-title":"Proc 28th Eur Solid-State Circuits Conf"},{"key":"ref3","first-page":"222","article-title":"Hardware countermeasures against DPA—A statistical analysis\n of their effectiveness","author":"mangard","year":"2004","journal-title":"Topics in Cryptology"},{"key":"ref6","first-page":"76","article-title":"Pinpointing the side-channel leakage of masked AES hardware implementation","year":"0","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref8","first-page":"81","article-title":"Evaluation of the masked logic style\n MDPL on a prototype chip","author":"popp","year":"0","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref7","article-title":"Random\n switching logic: A countermeasure against DPA based on transition probability","author":"suzuki","year":"2004","journal-title":"Cryptology ePrint Archive"},{"journal-title":"Power Analysis Attacks—Revealing the Secrets of Smart Cards","year":"2007","author":"mangard","key":"ref2"},{"key":"ref1","first-page":"388","article-title":"Differential\n power analysis","author":"kocher","year":"0","journal-title":"Proc 19th Ann Int Cryptology Conf Adv Cryptology"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1502781.1502784"},{"key":"ref20","first-page":"1","article-title":"Test vector leakage assessment (TVLA) methodology in practice","author":"cooper","year":"0","journal-title":"Proc Int Cryptographic Module Conf"},{"key":"ref22","first-page":"495","article-title":"Leakage assessment methodology—A clear roadmap for side-channel evaluations","author":"schnneider","year":"0","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref21","article-title":"A testing methodology for side channel\n resistance validation","author":"goodwill","year":"2011","journal-title":"NIST Non-invasive Attack Testing Workshop"}],"container-title":["IEEE Transactions on Dependable and Secure Computing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8858\/8452067\/07571149.pdf?arnumber=7571149","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T16:42:12Z","timestamp":1643215332000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7571149\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9,1]]},"references-count":22,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tdsc.2016.2610966","relation":{},"ISSN":["1545-5971","1941-0018","2160-9209"],"issn-type":[{"type":"print","value":"1545-5971"},{"type":"electronic","value":"1941-0018"},{"type":"electronic","value":"2160-9209"}],"subject":[],"published":{"date-parts":[[2018,9,1]]}}}