{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T23:55:51Z","timestamp":1773705351841,"version":"3.50.1"},"reference-count":76,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T00:00:00Z","timestamp":1772323200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T00:00:00Z","timestamp":1772323200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T00:00:00Z","timestamp":1772323200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Dependable and Secure Comput."],"published-print":{"date-parts":[[2026,3]]},"DOI":"10.1109\/tdsc.2025.3630054","type":"journal-article","created":{"date-parts":[[2025,11,6]],"date-time":"2025-11-06T18:55:47Z","timestamp":1762455347000},"page":"2774-2787","source":"Crossref","is-referenced-by-count":0,"title":["Coeus: Secure Similarity-Aware Data Integrity Verification for Secure Memories"],"prefix":"10.1109","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7881-3501","authenticated-orcid":false,"given":"Kazi Abu","family":"Zubair","sequence":"first","affiliation":[{"name":"North Carolina State University, Raleigh, NC, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-1233-4472","authenticated-orcid":false,"given":"Rahaf","family":"Abdullah","sequence":"additional","affiliation":[{"name":"North Carolina State University, Raleigh, NC, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3227-2505","authenticated-orcid":false,"given":"David","family":"Mohaisen","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Central Florida, Orlando, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9779-1838","authenticated-orcid":false,"given":"Tamara Silbergleit","family":"Lehman","sequence":"additional","affiliation":[{"name":"Electrical, Computer and Energy Engineering Department, University of Colorado Boulder, Boulder, CO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6050-0187","authenticated-orcid":false,"given":"Amro","family":"Awad","sequence":"additional","affiliation":[{"name":"Engineering Science Department, University of Oxford, Oxford, U.K."}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2023.3279031"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2020.3020085"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00043"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS53621.2022.00033"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2019.2941193"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3447818.3460377"},{"issue":"086","key":"ref7","first-page":"1","article-title":"Intel SGX explained","volume":"2016","author":"Costan","year":"2016","journal-title":"IACR Cryptology ePrint Arch."},{"key":"ref8","first-page":"1","article-title":"A memory encryption engine suitable for general purpose processors","volume-title":"Cryptology ePrint Arch.","author":"Gueron","year":"2016"},{"key":"ref9","article-title":"Method and apparatus for sharing security metadata memory space","author":"Chhabra","year":"2021"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00040"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"104","DOI":"10.1145\/3307650.3322250","article-title":"Triad-NVM: Persistency for integrity-protected and encrypted non-volatile memories","volume-title":"Proc. 46th Int. Symp. Comput. Architecture","author":"Awad","year":"2019"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"157","DOI":"10.1145\/3307650.3322252","article-title":"Anubis: Ultra-low overhead and recovery time for secure non-volatile memories","volume-title":"Proc. 46th Int. Symp. Comput. Architecture","author":"Zubair","year":"2019"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136502"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3177155"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00043"},{"key":"ref16","article-title":"8Gb C-die DDR4 SDRAM (K4A8G165WC), Rev. 1.5","year":"2017"},{"key":"ref17","article-title":"DDR4 SDRAM EDY4016A\u2014256Mb \u00d7 16 (4Gb: x16 DDR4 SDRAM features)","year":"2017"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872377"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00046"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.16"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00066"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783741"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00066"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465885"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00114"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062205"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3015925"},{"key":"ref28","first-page":"1","article-title":"No compromises: Secure NVM with crash consistency, write-efficiency and high-performance","volume-title":"Proc. 56th ACM\/IEEE Des. Automat. Conf.","author":"Yang","year":"2019"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2018.2863281"},{"key":"ref30","article-title":"The gem5 simulator: Version 20.0","author":"Lowe-Power","year":"2020"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2018.00028"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080232"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080230"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"143","DOI":"10.1145\/3307650.3322206","article-title":"Janus: Optimizing memory and storage support for non-volatile memory systems","volume-title":"Proc. Int. Symp. Comput. Architecture","author":"Liu","year":"2019"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516660"},{"key":"ref37","article-title":"AMD memory encryption","author":"Kaplan","year":"2021"},{"key":"ref38","article-title":"An architecture for the AES-GCM security standard","author":"Wang","year":"2006"},{"key":"ref39","first-page":"1","article-title":"A> 100 Gbps inline AES-GCM hardware engine and protected DMA transfers between SGX enclave and FPGA accelerator device.","volume":"2020","author":"Ghosh","year":"2020","journal-title":"IACR Cryptology ePrint Arch."},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2017.8335570"},{"key":"ref41","article-title":"Helion technology: AES-GCM IP cores for ASIC","year":"2014"},{"key":"ref42","article-title":"Intel data direct I\/O technology","year":"2020"},{"key":"ref43","first-page":"1","article-title":"Authentication weaknesses in GCM","author":"Ferguson","year":"2005","journal-title":"Comments Submitted NIST Modes Operation Process"},{"key":"ref44","first-page":"1","article-title":"AES-GCM-SIV: Specification and analysis","volume":"2017","author":"Gueron","year":"2017","journal-title":"IACR Cryptology ePrint Arch."},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566464"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071100"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2786763.2694387"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597655"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555777"},{"key":"ref50","article-title":"Introduction to memory bandwidth monitoring in the intel xeon processor E5 v4 family","year":"2016"},{"key":"ref51","article-title":"Arm architecture reference manual supplement memory system resource partitioning and monitoring (MPAM), for Armv8-A","year":"2016"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44647-8_19"},{"issue":"4","key":"ref53","first-page":"1","article-title":"Counter mode security: Analysis and recommendations","volume":"2","author":"McGrew","year":"2002","journal-title":"Cisco Syst., November"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/885651.781076"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/2810103.2813613"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.3390\/cryptography2030025"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/micro50266.2020.00015"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"ref59","article-title":"Intel xeon processor E5-2667 v2","year":"2013"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446722"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.111"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ICDCS.2019.00102"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/TCC.2015.2511752"},{"key":"ref64","first-page":"302","article-title":"Pageforge: A near-memory content-aware page-merging architecture","volume-title":"Proc. IEEE\/ACM Int. Symp. Microarchitecture","author":"Skarlatos","year":"2017"},{"key":"ref65","first-page":"377","article-title":"Base-Delta-immediate compression: Practical data compression for on-chip caches","volume-title":"Proc. Int. Conf. Parallel Architectures Compilation Techn","author":"Pekhimenko","year":"2012"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/2591635.2667184"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183547"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00041"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.11"},{"key":"ref70","first-page":"217","article-title":"Strong and efficient cache side-channel protection using hardware transactional memory","volume-title":"Proc. 26th USENIX Secur. Symp.","author":"Gruss","year":"2017"},{"key":"ref71","first-page":"955","article-title":"Translation leak-aside buffer: Defeating cache side-channel protections with TLB attacks","volume-title":"Proc. 27th USENIX Secur. Symp.","author":"Gras","year":"2018"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.5555\/3241094.3241161"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358310"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480067"},{"key":"ref75","first-page":"347","article-title":"Migratable Merkle trees for efficient distributed secure memory","volume-title":"Proc. IEEE Int. Symp. High- Perform. Comput. Architecture","author":"Feng","year":"2023"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3134098"}],"container-title":["IEEE Transactions on Dependable and Secure Computing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8858\/11434575\/11231112.pdf?arnumber=11231112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T22:52:45Z","timestamp":1773701565000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11231112\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3]]},"references-count":76,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tdsc.2025.3630054","relation":{},"ISSN":["1545-5971","1941-0018","2160-9209"],"issn-type":[{"value":"1545-5971","type":"print"},{"value":"1941-0018","type":"electronic"},{"value":"2160-9209","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,3]]}}}