{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:32:46Z","timestamp":1729665166343,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tencon.2018.8650219","type":"proceedings-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T17:10:38Z","timestamp":1552929038000},"page":"1489-1492","source":"Crossref","is-referenced-by-count":0,"title":["A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity"],"prefix":"10.1109","author":[{"given":"Naoki","family":"Fujieda","sequence":"first","affiliation":[]},{"given":"Yusuke","family":"Ayuzawa","sequence":"additional","affiliation":[]},{"given":"Masato","family":"Hongo","sequence":"additional","affiliation":[]},{"given":"Shuichi","family":"Ichikawa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.2307\/2007970"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.1002\/9780470127896","author":"kilts","year":"2007","journal-title":"Advanced FPGA Design Architecture Implementation and Optimization"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E94.A.211"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/359340.359342"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.151"},{"key":"ref5","first-page":"150","article-title":"Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor","author":"oliver","year":"2004","journal-title":"Proc 31st Ann Int'l Symp Computer Architecture (ISCA)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1190586"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.10.013"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"270","DOI":"10.1016\/j.micpro.2013.01.001","article-title":"An FPGA based high performance optical flow hardware design for computer vision applications","volume":"37","author":"gultekin","year":"2013","journal-title":"Microprocessors and Microsystems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IC-NC.2010.56"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/12.936241"}],"event":{"name":"TENCON 2018 - 2018 IEEE Region 10 Conference","start":{"date-parts":[[2018,10,28]]},"location":"Jeju, Korea (South)","end":{"date-parts":[[2018,10,31]]}},"container-title":["TENCON 2018 - 2018 IEEE Region 10 Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8643125\/8650051\/08650219.pdf?arnumber=8650219","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,14]],"date-time":"2023-09-14T12:43:42Z","timestamp":1694695422000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8650219\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/tencon.2018.8650219","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}