{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T08:23:17Z","timestamp":1771489397230,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T00:00:00Z","timestamp":1761523200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T00:00:00Z","timestamp":1761523200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["RS-2025-02653773"],"award-info":[{"award-number":["RS-2025-02653773"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,27]]},"DOI":"10.1109\/tencon66050.2025.11375042","type":"proceedings-article","created":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T21:13:38Z","timestamp":1771449218000},"page":"449-453","source":"Crossref","is-referenced-by-count":0,"title":["Design of Highly Stackable Charge Trap-Based 3D DRAM"],"prefix":"10.1109","author":[{"given":"Hyeongyu","family":"Kim","sequence":"first","affiliation":[{"name":"Jeonbuk National University,Division of Electronic Engineering,Jeonju,Jeonbuk,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dabok","family":"Lee","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Gyeongsang National University,Jinju,Gyeongnam,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyun-Sik","family":"Choi","sequence":"additional","affiliation":[{"name":"Electronic Materials Engineering, Kwangwoon University,Seoul,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoojin","family":"Seol","sequence":"additional","affiliation":[{"name":"Jeonbuk National University,Division of Electronic Engineering,Jeonju,Jeonbuk,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jonghyeon","family":"Ha","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Gyeongsang National University,Jinju,Gyeongnam,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kihyun","family":"Kim","sequence":"additional","affiliation":[{"name":"Jeonbuk National University,Division of Electronic Engineering,Jeonju,Jeonbuk,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jungsik","family":"Kim","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Gyeongsang National University,Jinju,Gyeongnam,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Won-Ju","family":"Cho","sequence":"additional","affiliation":[{"name":"Electronic Materials Engineering, Kwangwoon University,Seoul,Rep. of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zvi","family":"Or-Bach","sequence":"additional","affiliation":[{"name":"MonolithIC3D,United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung-Il","family":"Chang","sequence":"additional","affiliation":[{"name":"MonolithIC3D,United States"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185290"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2024.3367800"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19574.2021.9720596"},{"key":"ref4","article-title":"First Demonstration of Innovative 3D ANDType Fully-Parallel Convolution Block with Ultra-High Areaand Energy-Efficiency","author":"Kim","year":"2023","journal-title":"IEEE IEDM, San Francisco, CA, USA"},{"key":"ref5","first-page":"222","article-title":"Performance breakthrough in NOR flash memory with dopant-segregated Schottky-barrier (DSSB) SONOS devices","volume-title":"IEEE Symposium on VLSI Technology","author":"Choi"},{"key":"ref6","article-title":"A 1.67 Tb, 5b\/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a $23.3 ~\\text{Gb} \/ \\text{mm} 2$ Bit Density","author":"Khakifirooz","year":"2023","journal-title":"IEEE ISSCC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409618"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3390\/nano12040628"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1063\/1.3078279"}],"event":{"name":"TENCON 2025 - 2025 IEEE Region 10 Conference (TENCON)","location":"Kota Kinabalu, Malaysia","start":{"date-parts":[[2025,10,27]]},"end":{"date-parts":[[2025,10,30]]}},"container-title":["TENCON 2025 - 2025 IEEE Region 10 Conference (TENCON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11373911\/11374914\/11375042.pdf?arnumber=11375042","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T07:30:49Z","timestamp":1771486249000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11375042\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,27]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/tencon66050.2025.11375042","relation":{},"subject":[],"published":{"date-parts":[[2025,10,27]]}}}