{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:47:05Z","timestamp":1759146425955,"version":"3.28.0"},"reference-count":21,"publisher":"Int. Test Conference","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.1994.528006","type":"proceedings-article","created":{"date-parts":[[2002,12,17]],"date-time":"2002-12-17T15:47:48Z","timestamp":1040140068000},"page":"614-623","source":"Crossref","is-referenced-by-count":13,"title":["A hybrid fault simulator for synchronous sequential circuits"],"prefix":"10.1109","author":[{"given":"R.","family":"Krieger","sequence":"first","affiliation":[]},{"given":"B.","family":"Becker","sequence":"additional","affiliation":[]},{"given":"M.","family":"Keim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.76937"},{"journal-title":"Computers and Intractability - A Guide to NP-Completeness","year":"1979","author":"garey","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185327"},{"journal-title":"Switching and Finite Automata Theory","year":"1978","author":"kohavi","key":"ref13"},{"journal-title":"test_circ Ein abstrakter Datentyp zur Representation von hierarchischen Schaltkreisen","year":"1993","author":"krieger","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1992.205971"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227782"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/12.144618"},{"key":"ref18","first-page":"143","article-title":"The sequential ATPG: A theoretical limit","author":"miczo","year":"1983","journal-title":"Int'l Test Conf"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ETC.1993.246566"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114826"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1993.669662"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1990.136694"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.76938"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/54.2032","article-title":"Designing circuits with partial scan","volume":"5","author":"agrawal","year":"1988","journal-title":"IEEE Design & Test of Comp"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675267"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/BF00971937"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185302"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185328"}],"event":{"name":"International Test Conference","acronym":"TEST-94","location":"Washington, DC, USA"},"container-title":["Proceedings., International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx2\/4035\/11581\/00528006.pdf?arnumber=528006","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T12:30:29Z","timestamp":1497529829000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/528006\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/test.1994.528006","relation":{},"subject":[]}}