{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T12:41:59Z","timestamp":1725712919347},"reference-count":2,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2002.1041772","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T23:36:53Z","timestamp":1056584213000},"page":"297-300","source":"Crossref","is-referenced-by-count":2,"title":["Verification of device interface hardware interconnections prior to the start of testing"],"prefix":"10.1109","author":[{"given":"G.","family":"Peterson","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"2","first-page":"2","article-title":"Catalyst digital subsystem programming","year":"1999","journal-title":"Image Answers V6 4"},{"key":"1","first-page":"292","article-title":"Digital signal integrity: Modeling and simulation with interconnects and packages","author":"young","year":"2001"}],"event":{"name":"2002 International Test Conference","acronym":"TEST-02","location":"Baltimore, MD, USA"},"container-title":["Proceedings. International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8073\/22329\/01041772.pdf?arnumber=1041772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T22:19:46Z","timestamp":1489443586000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1041772\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":2,"URL":"https:\/\/doi.org\/10.1109\/test.2002.1041772","relation":{},"subject":[]}}