{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:30:41Z","timestamp":1758893441687,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2002.1041850","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T23:36:53Z","timestamp":1056584213000},"page":"947-953","source":"Crossref","is-referenced-by-count":9,"title":["Charge based transient current testing (CBT) for submicron CMOS SRAMs"],"prefix":"10.1109","author":[{"given":"B.","family":"Alorda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Rosales","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Soden","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Hawkins","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Segura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"32","article-title":"Idd pulse response testing applied to complex CMOS ICs","author":"beasley","year":"1997","journal-title":"Int Test Conf (ITC)"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012650"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008222623441"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805613"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805615"},{"key":"13","first-page":"90","article-title":"Neighbor selection for variance reduction in IDDQ and other parametric data","author":"daasch","year":"2001","journal-title":"Int Test Conf (ITC)"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529922"},{"key":"11","first-page":"738","article-title":"Current ratios: A self-scaling technique for production IDDQ testing","author":"maxwell","year":"1999","journal-title":"Int Test Conf (ITC)"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805800"},{"key":"21","doi-asserted-by":"crossref","first-page":"1668","DOI":"10.1049\/el:19941168","article-title":"built-in dynamic current sensor circuit for digital vlsi cmos testing","volume":"30","author":"segura","year":"1994","journal-title":"Electronics Letters"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639590"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1049\/el:19990359"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923451"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030215"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1007\/BF00993086"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/4.634662"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/IDDQ.1997.633013"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968689"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/43.992767"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527983"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313908"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/4.859508"},{"key":"1","first-page":"136","article-title":"Intrinsic leakage in low power deep submicron CMOS ICs","author":"kesharavarzi","year":"1997","journal-title":"Int Test Conf (ITC)"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041749"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557153"},{"journal-title":"High Speed CMOS Design Styles","year":"1998","author":"bernstein","key":"5"},{"journal-title":"Design of High-Performance Microprocessor Circuits","year":"2001","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/4.859508"},{"key":"8","first-page":"1186","article-title":"Impact of spatial intrachip gate length variability on the performance of hi-speed digital circuits","volume":"35","author":"orshansky","year":"2000","journal-title":"IEEE J of Solid State Circuits"}],"event":{"name":"2002 International Test Conference","acronym":"TEST-02","location":"Baltimore, MD, USA"},"container-title":["Proceedings. International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8073\/22329\/01041850.pdf?arnumber=1041850","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:43:44Z","timestamp":1497566624000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1041850\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/test.2002.1041850","relation":{},"subject":[]}}