{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T14:28:30Z","timestamp":1743344910495,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2002.1041870","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T19:36:53Z","timestamp":1056569813000},"page":"1130-1139","source":"Crossref","is-referenced-by-count":4,"title":["A DFT technique for low frequency delay fault testing in high performance digital circuits"],"prefix":"10.1109","author":[{"given":"B.","family":"Chatterjee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Sachdev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Keshavarzi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/4.962283"},{"key":"16","first-page":"192","article-title":"470ps 64-bit parallel adder","author":"park","year":"2000","journal-title":"IEEE VLSI Circuits Symp"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/92.863622"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/82.539001"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5573-5"},{"key":"12","first-page":"181","article-title":"On effective IDDQ testing of low voltage CMOS circuits using leakage control techniques","author":"cheng","year":"2000","journal-title":"Proc IEEE Int Symp Quality Electron Design"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743133"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639727"},{"journal-title":"International technology roadmap for semiconductors 2001 edition","year":"2001","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2355-0"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805641"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529854"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639607"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470686"},{"key":"9","doi-asserted-by":"crossref","first-page":"1279","DOI":"10.1109\/82.885134","article-title":"Design-for-testability for detecting delay faults in CMOS\/ BiCMOS logic families","volume":"47","author":"raahemifar","year":"2000","journal-title":"IEEE Trans on Circuits and Systems - II Analog and Digital Signal Processing"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/4.62148"}],"event":{"name":"2002 International Test Conference","acronym":"TEST-02","location":"Baltimore, MD, USA"},"container-title":["Proceedings. International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8073\/22329\/01041870.pdf?arnumber=1041870","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,24]],"date-time":"2018-02-24T18:41:10Z","timestamp":1519497670000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1041870\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/test.2002.1041870","relation":{},"subject":[]}}