{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T14:00:14Z","timestamp":1742392814996,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2003.1270823","type":"proceedings-article","created":{"date-parts":[[2004,7,8]],"date-time":"2004-07-08T16:05:44Z","timestamp":1089302744000},"page":"39-47","source":"Crossref","is-referenced-by-count":14,"title":["Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories"],"prefix":"10.1109","volume":"1","author":[{"given":"D.","family":"Wright","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Sachdev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1997.621492"},{"key":"2","first-page":"583","article-title":"0.8V CMOS Content-Addressable-Memory (CAM) Cell Circuit With A Fast Tag-Compare Capability Using Bulk PMOS Dynamic-Threshold (BP-DTMOS) Technique Based On Standard CMOS Technology for Low-Voltage VLSI Systems","author":"shen","year":"2002","journal-title":"IEEE International Symposium on Circuits and Systems"},{"journal-title":"MOSAID Class-IC DC9288 Feature Sheet","year":"2003","key":"10"},{"key":"1","first-page":"57","article-title":"A CAM Memory for 10Gbit and Terabit Routers and Switches","volume":"72","author":"schultz","year":"2000","journal-title":"Electronic Engineering"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.1999.782688"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1998.670899"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.1998.705951"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954697"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.1994.397199"},{"key":"8","first-page":"577","article-title":"Testing Content-Addressable Memories Using Functional Fault Models and March-Like Algorithms","author":"lin","year":"2000","journal-title":"IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1991.208150"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/54.748805"}],"event":{"name":"International Test Conference, 2003. ITC 2003.","location":"Washington, DC, USA"},"container-title":["International Test Conference, 2003. Proceedings. ITC 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8970\/28457\/01270823.pdf?arnumber=1270823","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T12:56:24Z","timestamp":1489409784000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270823\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/test.2003.1270823","relation":{},"subject":[]}}