{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:27:49Z","timestamp":1742383669905},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2004.1386933","type":"proceedings-article","created":{"date-parts":[[2005,3,21]],"date-time":"2005-03-21T15:07:39Z","timestamp":1111417659000},"page":"23-30","source":"Crossref","is-referenced-by-count":4,"title":["AC IO loopback design for high speed \u03bcprocessor IO test"],"prefix":"10.1109","author":[{"given":"B.","family":"Provost","sequence":"first","affiliation":[]},{"given":"T.","family":"Huang","sequence":"additional","affiliation":[]},{"given":"C.H.","family":"Lim","sequence":"additional","affiliation":[]},{"given":"K.","family":"Tian","sequence":"additional","affiliation":[]},{"given":"M.","family":"Bashir","sequence":"additional","affiliation":[]},{"given":"M.","family":"Atha","sequence":"additional","affiliation":[]},{"given":"A.","family":"Muhtaroglu","sequence":"additional","affiliation":[]},{"given":"C.","family":"Zhao","sequence":"additional","affiliation":[]},{"given":"H.","family":"Muljono","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542317"},{"key":"ref3","first-page":"130","article-title":"Designing a 3 GHr, 130 nm, Intel® Pentium® 4 processor","author":"deleganes","year":"0","journal-title":"Proc 2002 VLSI Circuits Symp"},{"article-title":"Method and Apparatus for Precise Signal Interpolation","year":"2003","author":"wang","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818295"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015058"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.688089"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818293"},{"key":"ref9","article-title":"A fully digitally controlled delay element with wide delay tuning range and small tuning error","author":"zhao","year":"0","journal-title":"US patent pending"},{"key":"ref1","article-title":"Elimination of Traditional Functional Testing of Interface Timings at Intel","author":"tripp","year":"0","journal-title":"ITC 2003"}],"event":{"name":"International Test Conference 2004","acronym":"TEST-04","location":"Charlotte, NC, USA"},"container-title":["2004 International Conferce on Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9526\/30190\/01386933.pdf?arnumber=1386933","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T19:54:41Z","timestamp":1489521281000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1386933\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/test.2004.1386933","relation":{},"subject":[]}}