{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:54:39Z","timestamp":1747810479235},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2004.1386988","type":"proceedings-article","created":{"date-parts":[[2005,3,21]],"date-time":"2005-03-21T20:07:39Z","timestamp":1111435659000},"page":"518-524","source":"Crossref","is-referenced-by-count":22,"title":["An economic analysis and ROI model for nanometer test"],"prefix":"10.1109","author":[{"given":"B.","family":"Keller","sequence":"first","affiliation":[]},{"given":"M.","family":"Tegethoff","sequence":"additional","affiliation":[]},{"given":"T.","family":"Bartenstein","sequence":"additional","affiliation":[]},{"given":"V.","family":"Chickermane","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033794"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966644"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041773"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270902"},{"key":"ref4","article-title":"Defect-Based Test: A Key Enabler for Successful Migration to Structural Test","author":"sengupta","year":"1999","journal-title":"Intel Technology Journal Ist quarter"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1992.527878"},{"journal-title":"SEMI Int'l Semiconductor Manufacturing Science Symposium","article-title":"Yield models in a Design for Manufacturing Environment: A Bibliography","year":"1993","key":"ref6"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2003","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/41.19069"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/54.980051"},{"year":"1993","key":"ref2","article-title":"IDDQ Testing of VLSI circuits"},{"year":"1990","key":"ref1","article-title":"Digital Systems Testing and Testable Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966696"}],"event":{"name":"International Test Conference 2004","acronym":"TEST-04","location":"Charlotte, NC, USA"},"container-title":["2004 International Conferce on Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9526\/30190\/01386988.pdf?arnumber=1386988","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T01:05:42Z","timestamp":1489539942000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1386988\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/test.2004.1386988","relation":{},"subject":[]}}