{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T15:49:15Z","timestamp":1742399355462,"version":"3.28.0"},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2004.1387002","type":"proceedings-article","created":{"date-parts":[[2005,3,7]],"date-time":"2005-03-07T13:32:27Z","timestamp":1110202347000},"page":"645-654","source":"Crossref","is-referenced-by-count":3,"title":["Application-dependent diagnosis of FPGAs"],"prefix":"10.1109","author":[{"given":"M.","family":"Baradaran Tahoori","sequence":"first","affiliation":[]}],"member":"263","reference":[{"journal-title":"Xilinx Easypath Solutions","year":"2003","key":"ref39"},{"journal-title":"The Programmable Logic Data Book 2003","year":"2003","key":"ref38"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"678","DOI":"10.1145\/775832.776003","article-title":"Using Satisfiability in Application Dependent Testing of FPGA Interconnects","author":"b tahoori","year":"2003","journal-title":"Proc Design Automation Conference"},{"key":"ref32","article-title":"Automatic Test Configuration Generation for FPGA Interconnect Testing","author":"b tahoori","year":"2003","journal-title":"Proc IEEE VLSI Test Symposium"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299239"},{"key":"ref30","article-title":"Novel Technique for Built-In-Self Test of FPGA Interconnects","author":"sun","year":"2000","journal-title":"Proc of Int‘l Test Conf"},{"key":"ref37","first-page":"722","article-title":"Test and diagnosis of faulty logic blocks in FPGAs","author":"j wang","year":"1997","journal-title":"Proc ICCAD"},{"key":"ref36","first-page":"52","article-title":"Interconnect Testing with Boundary Scan","author":"t wagner","year":"1987","journal-title":"Proc Int‘l Test Conf"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2002.1188703"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250138"},{"key":"ref10","first-page":"49","article-title":"Interconnect Testing in Cluster-Based FGPA Architectures","author":"harris","year":"2000","journal-title":"Proc DAC"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741625"},{"key":"ref11","first-page":"472","article-title":"Diagnosis of Interconnect Faults in Cluster-Based FGPA Architectures","author":"harris","year":"2000","journal-title":"Proc ICCAD"},{"key":"ref12","article-title":"Column-Based Precompiled Configuration Techniques for FPGA Fault Tolerance","author":"huang","year":"2001","journal-title":"Proc of IEEE Symp on Field-Programmable Custom Computing Machines"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.678888"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510859"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/54.655181"},{"key":"ref16","first-page":"63","article-title":"A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Networks","author":"jarwala","year":"1989","journal-title":"Proc of Int‘l Test Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1995.512646"},{"key":"ref18","first-page":"100","article-title":"Diagnosing Programmable Interconnect Systems for FPGAs","author":"f","year":"1996","journal-title":"Proc Int‘l Symp on FPGAs"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223950"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639662"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.808508"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743180"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1999.745159"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1999.810777"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510883"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801609"},{"key":"ref8","first-page":"83","article-title":"Electronic Chip-in Place Test","author":"goel","year":"1982","journal-title":"Proc of Int‘l Test Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.9188"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"391","DOI":"10.1126\/science.285.5426.391","article-title":"Electronically Configurable Molecular-Based Logic Gates","volume":"285","author":"collier","year":"1999","journal-title":"Science"},{"key":"ref9","article-title":"Digital Logic Using Molecular Electronics","author":"goldstein","year":"2002","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1109\/TEST.2000.894275","article-title":"BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs","author":"abramovici","year":"2000","journal-title":"Proc Int’ 1 Test Conf"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1996.555139"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.777814"},{"key":"ref21","article-title":"Fault Location in FPGA-Based Reconfigurable Systems","author":"mitra","year":"1998","journal-title":"Proc IEEE Int Workshop High-Level Design Validation and Test"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894292"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966716"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"430","DOI":"10.1109\/92.407000","article-title":"Optimal Interconnect Diagnosis of Wiring Networks","volume":"3","author":"shi","year":"1995","journal-title":"IEEE Trans on VLSI"},{"key":"ref25","first-page":"83","article-title":"Testing Computer Hardware through Data Compression in Space and Time","author":"k k","year":"1983","journal-title":"Proc Int‘l Test Conf"}],"event":{"name":"International Test Conference 2004","acronym":"TEST-04","location":"Charlotte, NC, USA"},"container-title":["2004 International Conferce on Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9526\/30190\/01387002.pdf?arnumber=1387002","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,7,6]],"date-time":"2021-07-06T10:47:11Z","timestamp":1625568431000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1387002\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/test.2004.1387002","relation":{},"subject":[]}}