{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T05:30:44Z","timestamp":1725600644749},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2004.1387379","type":"proceedings-article","created":{"date-parts":[[2005,3,21]],"date-time":"2005-03-21T20:07:39Z","timestamp":1111435659000},"page":"1061-1071","source":"Crossref","is-referenced-by-count":3,"title":["A hierarchical DFT architecture for chip, board and system test\/debug"],"prefix":"10.1109","author":[{"given":"C.A.","family":"Njinda","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1989.56808"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307577"},{"key":"ref12","first-page":"106","article-title":"TRIBuTE™ Board and Platform Test Methodology","author":"nejedlo","year":"2003","journal-title":"Proc IEEE International Test Conference"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271201"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0367-5"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041869"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041855"},{"key":"ref17","first-page":"167","article-title":"Backplane Test Bus Applications","author":"gibbs","year":"2003","journal-title":"Proc IEEE International Test Conference"},{"journal-title":"Mentor Graphics Corporation","article-title":"Fastscan and FlexTest Reference Manual","year":"0","key":"ref18"},{"journal-title":"Agilent Technologies","article-title":"Agilent 93000 SOC Series","year":"0","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041825"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805812"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510868"},{"key":"ref5","first-page":"141","article-title":"Test and On-line Debug Capabilities of IEEE 1149.1 in UltraSPARC™- III Microprocessor","author":"golshan","year":"2000","journal-title":"Proc IEEE International Test Conference"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743348"},{"key":"ref7","first-page":"140","article-title":"Instruction Based BIST for Board\/System Level Test of External Memories and Interconnects","author":"caty","year":"2003","journal-title":"Proc IEEE International Test Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529829"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639644"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966630"}],"event":{"name":"International Test Conference 2004","acronym":"TEST-04","location":"Charlotte, NC, USA"},"container-title":["2004 International Conferce on Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9526\/30190\/01387379.pdf?arnumber=1387379","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T01:28:51Z","timestamp":1489541331000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1387379\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/test.2004.1387379","relation":{},"subject":[]}}