{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:10:46Z","timestamp":1762251046051},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2004.1387387","type":"proceedings-article","created":{"date-parts":[[2005,3,21]],"date-time":"2005-03-21T15:07:39Z","timestamp":1111417659000},"page":"1128-1137","source":"Crossref","is-referenced-by-count":15,"title":["Speed clustering of integrated circuits"],"prefix":"10.1109","author":[{"given":"K.A.","family":"Brand","sequence":"first","affiliation":[]},{"given":"S.","family":"Mitra","sequence":"additional","affiliation":[]},{"given":"E.","family":"Volkerink","sequence":"additional","affiliation":[]},{"given":"E.J.","family":"McCluskey","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"R.E.A.L. DSP technology for telecom broadband processing","author":"p","year":"1998","journal-title":"Proc lntl Conf Signal Processing Applications and Technology"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1992.232745"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805610"},{"key":"ref13","first-page":"69","article-title":"Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies","author":"r","year":"2002","journal-title":"Proc IEEE VLS1 Test Symp"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966738"},{"key":"ref15","first-page":"43","article-title":"Delay Defect Screening using Process Monitor Structures","author":"s","year":"2004","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207761"},{"key":"ref17","first-page":"592","article-title":"An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit","author":"w","year":"2003","journal-title":"Proc Intl Test Conf"},{"key":"ref18","first-page":"1","article-title":"Microprocessor reliability performance as a function of die location for a 0.25?, five layer metal CMOS logic process","author":"riordan","year":"1999","journal-title":"Proc Intl Reliability Physics Symp"},{"key":"ref19","first-page":"207","article-title":"Reliability versus yield and die location in deep sub-micron VLSI","author":"w","year":"2000","journal-title":"Int Symp Semiconductor Manufacturing"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1109\/TEST.2001.966652","article-title":"Multiple-Output Propagation Transition Fault Test","author":"tseng","year":"2001","journal-title":"Proc Intl Test Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743151"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1147\/rd.441.0112"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232255"},{"key":"ref29","first-page":"105","article-title":"Experiments in detecting delay Faults using multiple higher frequency clocks and results from neighboring die","author":"h","year":"2003","journal-title":"Proc Intl Test Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557111"},{"key":"ref8","first-page":"437","article-title":"Timing yield estimation from static timing analysis","author":"a","year":"2001","journal-title":"Proc Intl Symp Quality Electronic Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033795"},{"key":"ref2","article-title":"Process Variation","author":"boning","year":"2001","journal-title":"Design of High-Performance Microprocessor Circuits"},{"article-title":"Integrated Circuit Manufacturability: The Art of Process and Design Integration","year":"1998","author":"j","key":"ref9"},{"key":"ref1","first-page":"1,1 11","article-title":"Use of DFT techniques in speed grading a 1 GHz+ microprocessor","author":"d","year":"2002","journal-title":"Proc Intl Test Conf"},{"article-title":"Statistics for Dummies","year":"2003","author":"d","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519514"},{"key":"ref21","first-page":"974","article-title":"Finding a Small Set of Longest Testable Paths that Cover Every Gate","author":"m","year":"2002","journal-title":"Proc Intl Test Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639638"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1992.243564"},{"year":"2003","key":"ref26","article-title":"Research Needs in Test and Testability"},{"key":"ref25","first-page":"4","article-title":"Binning for IC quality: experimental studies on the SEMATECH data","author":"d","year":"1998","journal-title":"Proc Defect and Fault Tolerance in VLSI Systems"}],"event":{"name":"International Test Conference 2004","acronym":"TEST-04","location":"Charlotte, NC, USA"},"container-title":["2004 International Conferce on Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9526\/30190\/01387387.pdf?arnumber=1387387","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T13:34:15Z","timestamp":1497620055000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1387387\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/test.2004.1387387","relation":{},"subject":[]}}