{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T23:57:49Z","timestamp":1725407869004},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2004.1387457","type":"proceedings-article","created":{"date-parts":[[2005,3,21]],"date-time":"2005-03-21T15:07:39Z","timestamp":1111417659000},"page":"1448-1454","source":"Crossref","is-referenced-by-count":3,"title":["Elimination of traditional functional testing of interface timings at Intel"],"prefix":"10.1109","author":[{"given":"M.","family":"Tripp","sequence":"first","affiliation":[]},{"given":"T.M.","family":"Mak","sequence":"additional","affiliation":[]},{"given":"A.","family":"Meixner","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234324"},{"article-title":"Digital variable-delay circuit having voltage-mixing interpolator and methods of testing input\/output buffers using same","year":"2002","author":"mooney","key":"ref11"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"446","DOI":"10.1109\/TEST.2002.1041794","article-title":"Complete, Contactless I\/O Testing-Reaching the Boundary in Minimizing Digital IC Testing Cost","author":"sunter*","year":"2002","journal-title":"Proc Int Test Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2001.934239"},{"journal-title":"A 2 5Gb\/s Bidirectional Signaling Technology Hot Interconnects Symposium 5","year":"1997","author":"haycock","key":"ref14"},{"article-title":"Apparatus and methods for testing simultaneous hi-directional I\/O circuits","year":"2002","author":"haycock","key":"ref15"},{"key":"ref4","article-title":"Method and apparatus to structurally detect random defects that impact AC I\/O timings in an Input\/Output buffer","author":"tripp","year":"0","journal-title":"United State Patent"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041795"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743140"},{"journal-title":"Method and Apparatus for Buffer Self-Test and Characterization","year":"1997","author":"sine","key":"ref5"},{"article-title":"Method and apparatus for controlling compensated buffers","year":"1999","author":"ilkbahar","key":"ref8"},{"article-title":"Method and apparatus for conducting input\/output loop back tests using a local pattern generator and delay elements","year":"2002","author":"bates","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966740"},{"journal-title":"Intel® Pentium® 4 Processor data sheet","year":"0","key":"ref1"},{"article-title":"Method and apparatus for testing an I\/O buffer","year":"2003","author":"fought","key":"ref9"}],"event":{"name":"International Test Conference 2004","acronym":"TEST-04","location":"Charlotte, NC, USA"},"container-title":["2004 International Conferce on Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9526\/30190\/01387457.pdf?arnumber=1387457","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T13:34:16Z","timestamp":1497620056000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1387457\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/test.2004.1387457","relation":{},"subject":[]}}